The Effect of Substrate Doping on the Behaviour of a CMOS Electrothermal Frequency-Locked-Loop

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference

2007

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Abstract-This paper describes a new implementation of a CMOS electrothermal frequency-locked-loop (FLL), whose output frequency is determined by the temperature-dependent phase shift of an electrothermal filter (ETF). The FLL maintains a constant phase shift in the ETF, and as a result drives it with a signal whose frequency is a well-defined function of temperature. Compared to a previous implementation, the FLL described here has significantly more loop gain, less electrical phase-spread, and is more suitable for full integration. Measurements on 16 samples (from one batch) show that the temperature dependence of the FLL's output frequency agrees very well with the known thermal properties of bulk silicon. The untrimmed spread of this frequency is less than 0.45% (3 ) from 40 C to 100 C, which corresponds to a temperature-sensing inaccuracy of less than 0.7 C (3 ).Index Terms-Electrothermal filter, frequency-locked-loop, synchronous demodulator, temperature sensor.

Section: Introductionmentioning

confidence: 99%

Interface electronics for a CMOS electrothermal frequency-locked-loop

Zhang

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference

2007

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“…16, as well as the simulated characteristics. These characteristics were obtained by inverting (10) and then performing an 8th order least-squares polynomial fit on the measured data, i.e., the output of the PT-100 sensor and the decimated output of the chips. Due to their different geometries, the slope of their phase characteristics is significantly different.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…3) acts to balance the average charge accumulated by the integrator: (9) where is a number between 0 and 1, which represents as a weighted average of the two phase references, , and : (10) If and are close to 90 degrees, the cosine function can be linearized, leading to a linear relation between and :…”

Section: System Designmentioning

confidence: 99%

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A temperature-to-digital converter based on an optimized electrothermal filter

Kashmiri

Xia

ESSCIRC 2008 - 34th European Solid-State Circuits Conference

2008

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Abstract-This paper describes the design of a CMOS temperature-to-digital converter (TDC). It operates by measuring the temperature-dependent phase shift of an electrothermal filter (ETF). Compared to previous work, this TDC employs an ETF whose layout has been optimized to minimize the thermal phase spread caused by lithographic inaccuracy. To minimize electrical phase spread, the TDC's front-end consists of a wide bandwidth gain-boosted transconductor. The transconductor's output current is then digitized by a phase-domain 61 modulator whose phase-summing node is realized by a chopper demodulator. To minimize the residual offset caused by the demodulator's switching action, the demodulator is located at the virtual ground nodes established by the transconductor's gain-boosting amplifiers. Measurements on 16 samples (within one batch) show that the TDC has an untrimmed inaccuracy of less than 0.7 C (3 ) over the military range ( 55 C to 125 C).

“…At a given frequency, the amount of phase shift will be determined by the ETF's geometry and by the thermal diffusivity of bulk silicon. Since the latter is well defined, the accuracy of this phase shift will be mainly limited by lithographic inaccuracy [1,4].…”

Section: Introductionmentioning

confidence: 99%

A digitally-assisted electrothermal frequency-locked loop

Kashmiri

2009 Proceedings of ESSCIRC

2009

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a) Figure I. The analog FLL of (I], (a), and the digitally-assisted FLL, (b).(b) '------1 II. SYSTEM-LEVEL DESIGN In Fig. 1a, a simplified block diagram of an analog FLL of [1] is shown. The YCO drives the ETF as well as a synchronous demodulator, which detects the phase of the ETF's output signal. The output of the synchronous demodulator is then integrated by an analog filter, which drives the YCO. The loop locks when the demodulator's DC output is zero, corresponding to a YCO frequency fvco = .190at which the phase shift of the ETF's near-sinusoidal output is about 90°. The FLL's phase-frequency characteristic is thus locked to that of the ETF.A block diagram of the proposed digitally-assisted electrothermal FLL is shown in Fig. 1b. Besides a YCO and an ETF, it consists of a phase domain M: modulator (PDM:M), a DAC, and a digital filter. The YCO drives the ETF, whose phase shift is then digitized by the PDM:M [5,6]. The latter's bitstream output is then compared with a phase reference of 90°, and the resulting error signal is then Hz were achieved with the help of a large (1 IlF) off-chip capacitor. In the digitally-assisted FLL described here, the noise bandwidth is defined by a digital filter, resulting in a solution that is more amenable to CMOS integration.In the next section, the system-level design of a digitallyassisted electrothermal FLL is described. Section III provides an overview of the circuit, while the measurement results are presented in section IY. The paper ends with conclusions.