The effect of interface states on amorphous-silicon transistors

Ibaraki, Nobuki; Fukuda, K.; Takata, Hitoshi

doi:10.1109/16.40965

Cited by 20 publications

(11 citation statements)

References 4 publications

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“…These results compare favorably with other work on integrated a-Si:H and poly-Si TFTs using laser processing, which resulted in a-Si TFTs with field-effect mobility of ϳ0.9 cm 2 /V s and poly-Si TFTs with field-effect mobility of ϳ20 cm 2 /V s. 1 Note that conventional bottom-gate a-Si:H TFTs have field-effect mobility of ϳ1 cm 2 /V s, 3 and the typical result for top-gate a-Si:H TFT with SiN x as the gate dielectric, is a field-effect mobility of ϳ0.4 cm 2 /V s and ON/OFF current ratio of ϳ10 5 . 13 We know of no other comparable results of a-Si:H TFTs after such a high temperature ͑600-625°C͒ anneal step.…”

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confidence: 97%

Integration of amorphous and polycrystalline silicon thin-film transistors through selective crystallization of amorphous silicon

Pangal

Sturm

Wagner

1999

Applied Physics Letters

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Selective exposure of a hydrogenated amorphous silicon (a-Si:H) film to a room-temperature hydrogen plasma using a patterned masking layer and a subsequent anneal at 600 °C, results in patterned polycrystalline and amorphous silicon regions. However, most of the hydrogen in the amorphous silicon is lost, leading to severe degradation in its properties. In this letter, we report the rehydrogenation of amorphous silicon films following this anneal to give a-Si:H thin-film transistors with a mobility as high as 1.2 cm2/V s and ON/OFF current ratios of ∼106. This process was used to integrate amorphous and polycrystalline silicon transistors on a single substrate with only one more lithography and processing step than that required for a single type of transistor.

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confidence: 97%

Integration of amorphous and polycrystalline silicon thin-film transistors through selective crystallization of amorphous silicon

Pangal

Sturm

Wagner

1999

Applied Physics Letters

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“…Also, observed saturation region degradation for decreasing a-Si:H thickness [4], [5] can be directly related to two-dimensional (2-D) field effects inherent to the staggered-inverted structure typically used for a-Si:H AMLCD TFT's [6]. Importantly, our modeling shows that although saturation current decreases with decreasing a-Si:H thickness, linear region conductance improves due to the improved contact characteristics of thin channel devices.…”

Section: Introductionmentioning

confidence: 82%

High mobility tri-layer a-Si:H thin-film transistors with ultrathin active layer

Thomasson

Jackson

1997

IEEE Electron Device Lett.

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We show that hydrogenated amorphous silicon thinfilm transistors (a-Si:H TFT's) with active layer thickness of 13 nm perform better for display applications than devices with thicker 50-nm active layers. A direct comparison of a-Si:H TFT's fabricated using an i-stopper TFT structure shows that ultrathin active layers significantly improve the device characteristics. For a 5-m channel length TFT, the linear region (V V V DS = 0:1 V) and saturation region mobilities increase from 0.4 cm 2 /V1s and 0.7 cm 2 /V1s for a 50-nm thick active layer a-Si:H device to 0.7 cm 2 /V1s and 1.2 cm 2 /V1s for a 13-nm thick active layer a-Si:H layer device fabricated with otherwise identical geometry and processing.

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“…When the N to Si ratio in the top SiN= layer was 1.3, the mobility was independent of the a-Si:H thickness. When the N to Si ratio was lowered to 1.1, the mobility decreased drastically with the decrease of the a-Si:H thickness (26). The top SiN= layer in this work has a N to Si ratio greater than 1.6.…”

Section: N + Etch--thementioning

confidence: 91%

A Self‐aligned, Trilayer, a‐Si:H Thin Film Transistor Prepared from Two Photomasks

Kuo

1992

J. Electrochem. Soc.

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A new self-aligned TFT structure that requires two photomasks is described in this paper. Three process steps, i.e., the bacldight lithography, the top dielectric etch, and the n + etch, have been studied in detail. The finished ~ has transfer characteristics and Id -Vd curves similar to those of a TFT prepared from a more complicated conventional process. TFT structure parameters, such as the channel length, the a-Si:H thickness, the source/drain via size, and the contact resistance, affect the field effect mobility and the Io,/Io~ratio. These relations were examined. Including a Ta205 thin layer in the gate dielectric structure changes the device characteristics. The relation between the Ta20~ process and the device has been studied.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 169.233.5.201 Downloaded on 2015-01-03 to IP

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The effect of interface states on amorphous-silicon transistors

Cited by 20 publications

References 4 publications

Integration of amorphous and polycrystalline silicon thin-film transistors through selective crystallization of amorphous silicon

Integration of amorphous and polycrystalline silicon thin-film transistors through selective crystallization of amorphous silicon

High mobility tri-layer a-Si:H thin-film transistors with ultrathin active layer

A Self‐aligned, Trilayer, a‐Si:H Thin Film Transistor Prepared from Two Photomasks

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