2014
DOI: 10.1016/j.microrel.2014.07.011
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The effect of gate overlap on the device degradation in IGZO thin film transistors

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Cited by 3 publications
(2 citation statements)
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References 11 publications
(13 reference statements)
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“…5,8,13) In TAOS-TFTs, many researchers predicted the existence of hot carriers as one of the degradation models of device reliability from transfer characteristics and capacitancevoltage (C-V ) characteristics. [20][21][22][23][24][25][26][27][28][29][30][31][32][33][34] However, it is a discussion point as to whether the generation of hot carriers is possible or not because TAOS such as IGZO have an amorphous structure and exhibit relatively low mobility of around 10 cm 2 V −1 s −1 compared with poly-Si or sc-Si. When hot carriers are generated in TAOS-TFTs, photon emission should be observed.…”
mentioning
confidence: 99%
“…5,8,13) In TAOS-TFTs, many researchers predicted the existence of hot carriers as one of the degradation models of device reliability from transfer characteristics and capacitancevoltage (C-V ) characteristics. [20][21][22][23][24][25][26][27][28][29][30][31][32][33][34] However, it is a discussion point as to whether the generation of hot carriers is possible or not because TAOS such as IGZO have an amorphous structure and exhibit relatively low mobility of around 10 cm 2 V −1 s −1 compared with poly-Si or sc-Si. When hot carriers are generated in TAOS-TFTs, photon emission should be observed.…”
mentioning
confidence: 99%
“…The source and drain electrodes were made of a 150 nm thick Mo and all devices were finally annealed in an oven at 350°C for 1 h. The channel length and width of tested transistors were 10 μm and 54 μm, respectively. More detailed process was explained in our previous work [10]. A white halogen lamp ranging from 500 to 700 nm wavelength was used as a light source.…”
Section: Device Fabrication and Measurementmentioning
confidence: 99%