The design of dynamically reconfigurable datapath coprocessors

Abstract

Increasing nonrecurring engineering and mask costs are making it harder to turn to hardwired application specific integrated circuit (ASIC) solutions for high-performance applications. The volume required to amortize these high costs has been increasing, making it increasingly expensive to afford ASIC solutions for medium-volume products. This has led to designers seeking programmable solutions of varying sorts using these so-called programmable platforms. These programmable platforms span a large range from bit-level programmable field programmable gate arrays to word-level programmable application-specific, and in some cases even general-purpose processors. The programmability comes with a power and performance overhead. Attempts to reduce this overhead typically involve making some core hardwired ASIC like logic blocks accessible to the programmable elements. This paper presents one such hybrid solution in this space-a relatively simple processor with a dynamically reconfigurable datapath acting as an accelerating coprocessor. This datapath consists of hardwired function units and reconfigurable interconnect. We present a methodology for the design of these solutions and illustrate it with two complete case studies: an MPEG2 coder, and a GSM coder, to show how significant speedups can be obtained using relatively little hardware. This work is part of the MESCAL project, which is geared towards developing design environments for the development of application-specific platforms.

A general constraint-centric scheduling framework for spatial architectures

“…∀e, e , bx ∈ Bmutex|B(e, bx)&B(e , bx), γ(e) = γ(e ) (31) Additionally, architectural constraints require the total length in instructions of the vertex bundles mapped to the same node to be ≤ 32. This requires defining, for each bundle, the maximum bundle length λ(bv) as a function of the last send message of the vertex.…”

“…The fundamental insight of many specialization techniques is to "map" large regions of computation to the hardware, breaking away from instruction-byinstruction pipelined execution and instead adopting a spatial architecture paradigm. Pioneering examples include RAW [50], Wavescalar [46] and TRIPS [9], motivated primarily by performance, and recent energy-focused proposals include Tartan [39], CCA [10], PLUG [13,35], FlexCore [47], SoftHV [15], MESCAL [31], SPL [51], C-Cores [48], DySER [25,26], BERET [27], and NPU [20]. A fundamental problem in all spatial architectures is the 1 Majority of work completed while author was a PhD student at UT-Austin Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

Architecture-Driven Synthesis of Reconfigurable Cells

“…A design flow for a simple processor with a dynamically reconfigurable data-path acting as an accelerating co-processor for a specific application domain has been proposed in [6]. The authors reported significant speedup for accelerators that have data-path consisting of hardwired function units and reconfigurable interconnect.…”

Μεθοδολογίες Αυτοματοποιημένης Εξερεύνησης Και Σύνθεσης Επαναδιατάξιμων Συνεπεξεργαστών Υλικού

“…[120], [49]) are based on pre-defined interconnection structures and register allocations which limit the customization of the flexible datapath to the application's domain needs [32]. On the other hand, row-based architectures [119], [16], [121], [122] are synthesized according to: (i) the resource constraints (i.e. the number of processing elements) for the flexible datapath and (ii) the set of kernels that are going to be mapped.…”

“…A crossbar-based interconnection can be adopted as the one already presented in Section 4.3 or a specialized interconnection can be allocated according to the communication paths defined by the set of kernels. Specialized interconnections among various kernels can be generated using the techniques presented in [121], [122].…”