2023
DOI: 10.3390/s23218715
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The Design of a Low-Noise, High-Speed Readout-Integrated Circuit for Infrared Focal Plane Arrays

Yusong Mu,
Zilong Zhao,
Chong Chen
et al.

Abstract: This paper describes the design of a low-noise, high-speed readout-integrated circuit for use in InGaAs infrared focal plane arrays, and analyzes the working principle and noise index of the pixel circuit in detail. The design fully considers the dynamic range, noise, and power consumption of the pixel circuit in which a capacitance transimpedance amplifier structure is adopted as the input stage circuit, and chip fabrication via an XFAB 0.18 µm CMOS process is successfully realized. The ROIC adopts monolithic… Show more

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Cited by 1 publication
(3 citation statements)
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“…The BP neural network architecture employed in this study comprised an input layer, an output layer, and two hidden layers. The dimension of the input layer was [1,6], corresponding to the optimization variables for the grid ground plane. The dimension of the output layer was [1,201], matching the number of frequency points.…”
Section: Network Parameter Settingsmentioning
confidence: 99%
See 2 more Smart Citations
“…The BP neural network architecture employed in this study comprised an input layer, an output layer, and two hidden layers. The dimension of the input layer was [1,6], corresponding to the optimization variables for the grid ground plane. The dimension of the output layer was [1,201], matching the number of frequency points.…”
Section: Network Parameter Settingsmentioning
confidence: 99%
“…The dimension of the input layer was [1,6], corresponding to the optimization variables for the grid ground plane. The dimension of the output layer was [1,201], matching the number of frequency points. The S-parameters in the frequency domain were represented by a complex-valued function depending on frequency.…”
Section: Network Parameter Settingsmentioning
confidence: 99%
See 1 more Smart Citation