The design methodology and implementation of a first-generation CELL processor: a multi-core SoC

Pham, Dac; Behnen, E.; Bolliger, M.; Hofstee, H. Peter; Johns, C.; Kahle, J.; Kameyama, Atsushi; Keaty, J.; Le, Bob; Masubuchi, Yoshio; Posluszny, S.; Riley, M.; Suzuoki, M.; Wang, M.; Warnock, J.; Weitzel, S.; Wendel, D.; Yazawa, Kazuaki

doi:10.1109/cicc.2005.1568604

Cited by 15 publications

(8 citation statements)

References 3 publications

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“…For instance, the IBM POWER6 clock frequency can increase from 4 GHz to 6 GHz by rising V dd from 0.9V to 1.3V [35]. Similar trends were observed for the IBM Cell [29]. Increasing V dd is not the only way to increase the clock frequency.…”

Section: The Sequential Acceleratorsupporting

confidence: 74%

“…When this happens, the effective SACC area for dissipating heat is reduced, which requires lowering the power envelope hence voltage and clock frequency 4. For instance, the IBM POWER6 and Cell processors have been designed to have a short clock cycle in FO4 delays, and they use high-speed circuit techniques[35,29], whereas the Intel i7 core was optimized for performance per watt[22].…”

mentioning

confidence: 99%

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Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses

Michaud

Sazeides

Seznec

2010

Proceedings of the 7th ACM International Conference on Computing Frontiers

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As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to design processors featuring hundreds of general-purpose cores. However, though a large number of cores speeds up parallel code sections, Amdahl's law requires speeding up sequential sections too. We argue that it will become possible to dedicate a substantial fraction of the chip area and power budget to achieve high sequential performance. Current general-purpose processors contain a handful of cores designed to be continuously active and run in parallel. This leads to power and thermal constraints that limit the core's performance. We propose removing these constraints with a sequential accelerator (SACC). A SACC consists of several cores designed for ultimate sequential performance. These cores cannot run continuously. A single core is active at any time, the rest of the cores are inactive and power-gated. We migrate the execution periodically to another core to spread heat generation uniformly over the whole SACC area, thus addressing the temperature issue. The SACC will be viable only if it yields significant sequential performance. Migration-induced cache misses may limit performance gains. We propose some solutions to mitigate this problem. We also investigate a migration method using thermal sensors, such that the migration interval depends on the ambient temperature and the migration penalty is negligible under normal thermal conditions.

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Section: The Sequential Acceleratorsupporting

confidence: 74%

mentioning

confidence: 99%

Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses

Michaud

Sazeides

Seznec

2010

Proceedings of the 7th ACM International Conference on Computing Frontiers

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“…The CELL pro-cessor [16,5,6] from IBM, which is designed for streaming multimedia computations, features 8 synergistic processor elements (SPEs), each operating on fixed-width (128-bit) vectors with private SRAM scratchpads which are filled using DMA operations. The Signal-processing On-Demand Architecture (SODA) [11,12] for 3G wireless protocols has a global scratchpad memory and local scratchpad memory for each of its 4 SIMD processors.…”

Section: Scratchpad Memorymentioning

confidence: 99%

Vegas

Chou

Severance

Brant

et al. 2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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This paper presents VEGAS, a new soft vector architecture, in which the vector processor reads and writes directly to a scratchpad memory instead of a vector register file. The scratchpad memory is a more efficient storage medium than a vector register file, allowing up to 9× more data elements to fit into on-chip memory. In addition, the use of fracturable ALUs in VEGAS allow efficient processing of bytes, halfwords and words in the same processor instance, providing up to 4× the operations compared to existing fixedwidth soft vector ALUs. Benchmarks show the new VE-GAS architecture is 10× to 208× faster than Nios II and has 1.7× to 3.1× better area-delay product than previous vector work, achieving much higher throughput per unit area. To put this performance in perspective, VEGAS is faster than a leading-edge Intel processor at integer matrix multiply. To ease programming effort and provide full debug support, VEGAS uses a C macro API that outputs vector instructions as standard NIOS II/f custom instructions.

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“…The Cell BE combines an IBM PowerPC Processor Element (PPE) and eight Synergistic Processor Elements (SPEs) [20]. An integrated high-bandwidth bus called the Element Interconnect Bus (EIB) connects the processors and their ports to external memory and I/O devices.…”

Section: Cell Broadband Enginementioning

confidence: 99%

Pairwise Distance Matrix Computation for Multiple Sequence Alignment on the Cell Broadband Engine

Wirawan

Schmidt

Kwoh

2009

Lecture Notes in Computer Science

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Abstract. Multiple sequence alignment is an important tool in bioinformatics. Although efficient heuristic algorithms exist for this problem, the exponential growth of biological data demands an even higher throughput. The recent emergence of accelerator technologies has made it possible to achieve a highly improved execution time for many bioinformatics applications compared to general-purpose platforms. In this paper, we demonstrate how the PlayStation®3, powered by the Cell Broadband Engine, can be used as a computational platform to accelerate the distance matrix computation utilized in multiple sequence alignment algorithms.

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The design methodology and implementation of a first-generation CELL processor: a multi-core SoC

Cited by 15 publications

References 3 publications

Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses

Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses

Vegas

Pairwise Distance Matrix Computation for Multiple Sequence Alignment on the Cell Broadband Engine

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