The Data Vortex Optical Packet Switched Interconnection Network

Abstract

Abstract-A complete review of the data vortex optical packet switched (OPS) interconnection network architecture is presented. The distributed multistage network topology is based on a banyan structure and incorporates a deflection routing scheme ideally suited for implementation with optical components. An implemented 12-port system prototype employs broadband semiconductor optical amplifier switching nodes and is capable of successfully routing multichannel wavelength-division multiplexing packets while maintaining practically error-free signal integrity (BER 10 12 ) with median latencies of 110 ns. Packet contentions are resolved without the use of optical buffers via a distributed deflection routing control scheme. The entire payload path in the optical domain exhibits a capacity of nearly 1 Tb/s. Further experimental measurements investigate the OPS interconnection network's flexibility and robustness in terms of optical power dynamic range and network timing. Subsequent experimental investigations support the physical layer scalability of the implemented architecture and serve to substantiate the merits of the data vortex OPS network architectural paradigm. Finally, modified design considerations that aim to increase the network throughput and device-level performance are presented.Index Terms-Interconnection networks (multiprocessor), optical interconnections, packet switching, photonic switching systems, wavelength-division multiplexing.

The Role of Photonics in Future Computing and Data Centers

“…We compared the performance of rack to rack LIONS with other state-of-art rack to rack switches including the electrical switching network architecture employing flattened butterfly topology, the IBM-Corning's Optical Packet Switch for Supercomputers (OSMOSIS) and the Data Vortex optical switch [23]- [26]. Figures 12(a) and (b) show the effective bandwidth and the end-to-end latency of LI-ONS comparing with a flattened butterfly network under a 32-and 128-node for a message size of 128 bytes.…”

160Gb/s Serial Line Rates in a Monolithic Optoelectronic Multistage Interconnection Network

“…The operation is repeated to transform the 80Gb/s 2 7 -1 PRBS to a sequence at 160Gb/s with the appropriate delay in the second Mach Zehnder interferometer stage. For the bit at time interval t, the pseudo-random bit sequence at the doubled line rate may be derived as follows: PRBS 80Gb/s ( ½ t ) = { PRBS 40Gb/s ( t ) t odd PRBS 40Gb/s ( t + ½ 2 7 ) t even…”

“…The use of high efficacy III-V materials may ultimately allow additional transceiver integration for optical network within chip architectures. Recent work into discrete [5][6][7] and monolithic [8][9] multi-stage switching circuits using semiconductor optical amplifiers is indicating routes to tens of connections, each operating at up to 100Gb/s aggregate with nanosecond time-scale reconfigurability. Capacity scaling is achieved primarily through wavelength multiplexing [7,[9][10].…”

“…Recent work into discrete [5][6][7] and monolithic [8][9] multi-stage switching circuits using semiconductor optical amplifiers is indicating routes to tens of connections, each operating at up to 100Gb/s aggregate with nanosecond time-scale reconfigurability. Capacity scaling is achieved primarily through wavelength multiplexing [7,[9][10]. Higher line rate studies have been performed in the non-linear regime to realise all-optical logic, sophisticated demultiplexing functions and wavelength conversion [11][12][13].…”

Implementing an Optical QoS Encoding Scheme in an Optical Packet Switching Fabric Test-Bed

“…OPS has been shown as a scalable approach for routing high-bandwidth wavelength-division-multiplexed (WDM) traffic with characteristically low power and low latency [5]. The practical realization of OPS faces significant challenges, particularly with contention resolution which may be required as multiple packets attempt to egress simultaneously on the same link.…”