CAS 2005 Proceedings. 2005 International Semiconductor Conference, 2005.

DOI: 10.1109/smicnd.2005.1558829

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Testing of digital circuitry using Xilinx chipscope logic analyzer

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Cited by 7 publications

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“…There are several tools available for monitoring FPGA based systems, which include JHDL[ 4], ChipScope [5] and Identify [6].…”

Section: Introductionmentioning

confidence: 99%

Automated instrumentation of FPGA-based systems for system-level transaction monitoring

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2009

2009 International Symposium on System-on-Chip

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Modern FPGA-based systems are complex and dif ficult to verify. One approach to easing the verification problem and reducing perceived complexity is to use libraries of reusable functions. These reusable functions, known as intellectual prop erty blocks, are commonly created as netlists or RTL components.Complex systems can be created from IP blocks by using high level design environments. These tools define the types and semantics of component interfaces which permit systems to be debugged using system-level transaction monitoring. However, the insertion of on-chip monitoring circuitry is a manual process in FPGA design flows. In this paper we present an algorithm which exploits the high-level design environment to permit automatic instrumentation of designs. We demonstrate that the algorithm can harness existing HDL generation techniques and reduce the insertion and configuration effort required of the designer.

“…There are several tools available for monitoring FPGA based systems, which include JHDL[ 4], ChipScope [5] and Identify [6].…”

Section: Introductionmentioning

confidence: 99%

Automated instrumentation of FPGA-based systems for system-level transaction monitoring

¹

,

²

,

³

2009

2009 International Symposium on System-on-Chip

View full text Add to dashboard Cite

Modern FPGA-based systems are complex and dif ficult to verify. One approach to easing the verification problem and reducing perceived complexity is to use libraries of reusable functions. These reusable functions, known as intellectual prop erty blocks, are commonly created as netlists or RTL components.Complex systems can be created from IP blocks by using high level design environments. These tools define the types and semantics of component interfaces which permit systems to be debugged using system-level transaction monitoring. However, the insertion of on-chip monitoring circuitry is a manual process in FPGA design flows. In this paper we present an algorithm which exploits the high-level design environment to permit automatic instrumentation of designs. We demonstrate that the algorithm can harness existing HDL generation techniques and reduce the insertion and configuration effort required of the designer.

Architectural Comparison of Instruments for Transaction Level Monitoring of FPGA-Based Packet Processing Systems

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2009

2009 17th IEEE Symposium on Field Programmable Custom Computing Machines

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No abstract

Design, validation and FPGA implementation of a brushless DC motor speed controller

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2010

2010 17th IEEE International Conference on Electronics, Circuits and Systems

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No abstract

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