Temperature variable supply voltage for power reduction

Shakeri, K.; Meindl, J.D.

doi:10.1109/isvlsi.2002.1016877

Cited by 12 publications

(8 citation statements)

References 6 publications

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“…However, due to the temperature increase of the coolant, the temperature of heaters 1-4 of the lower tier are elevated by 4.9°C, 5.7°C, 7.8°C, and 9.7°C, respectively. Vertical thermal coupling may cause idle tiers to get warmer, leading to unwanted leakage power [23]. To reduce the vertical thermal coupling between tiers in microfluidic cooling, each tier can have its own MFHS (Case C) instead of sharing one heat sink (Case B).…”

Section: B Vertical Thermal Couplingmentioning

confidence: 99%

“…This section discusses the leakage power for different cores along the coolant flow direction. The main contributor to leakage current is subthreshold current (I sub ) given by [23] …”

Section: Electrical Implicationsmentioning

confidence: 99%

“…V T is the thermal voltage; V GS and V TH are the gate-source current and the threshold voltage, respectively. With (11) [23] and assuming the supply voltage does not change dynamically, the leakage power is calculated for a single tier with uniform power and lateral thermal gradient due to fluidic coolant temperature gradient from the inlet to the outlet (i.e., as discussed in Fig. 10).…”

Section: Electrical Implicationsmentioning

confidence: 99%

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3-D Stacked Tier-Specific Microfluidic Cooling for Heterogeneous 3-D ICs

Zhang

Zheng

Bakir

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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Cooling is a significant challenge for highperformance and high-power 3-D ICs. In this paper, tier-specific microfluidic cooling technology is proposed and experimentally evaluated in a 3-D stack. Different stacking scenarios are experimentally evaluated including: 1) a memory-on-processor stack; 2) a processor-on-processor stack with equal power dissipation; 3) a processor-on-processor stack with different power dissipations; and 4) a two-tier 3-D stack with each tier containing four cores along the flow direction. Compared with conventional microfluidic cooling, the tier-specific cooling is shown to reduce the pumping power by 37.5% by preventing overcooling when an operating temperature is specified. The results are benchmarked with an air-cooled heat sink. The impact of the lateral thermal gradient along the flow direction on the electrical performances, including leakage power and clock frequency, is analyzed.Index Terms-3-D IC, leakage power, microchannel heat sink, micropin-fin (MPF) heat sink, multicore processors.

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Section: B Vertical Thermal Couplingmentioning

confidence: 99%

“…This section discusses the leakage power for different cores along the coolant flow direction. The main contributor to leakage current is subthreshold current (I sub ) given by [23] …”

Section: Electrical Implicationsmentioning

confidence: 99%

Section: Electrical Implicationsmentioning

confidence: 99%

See 1 more Smart Citation

3-D Stacked Tier-Specific Microfluidic Cooling for Heterogeneous 3-D ICs

Zhang

Zheng

Bakir

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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“…In this paper, we propose a combination of two methods to ensure compensation against delay variations: varying buffer strength and controlling interconnect delay. First approach makes use of the fact that temperature gradient affects threshold voltage and mobility, which can also be controlled through bias voltages, V DD [15]. This would require temperature sensors and level converters.…”

Section: B Measurementsmentioning

confidence: 99%

Timing analysis for thermally robust clock distribution network design for 3D ICs

Park

Natu

Swaminathan

et al. 2013

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems

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Three-dimensional Integrated Circuits provide a solution to overcome bottlenecks in performance and power management issues. However, the drawback arises in the form of increased thermal density that results in thermal gradients that affect signal integrity. Since, the clock signal is critical for ensuring the performance of synchronous digital systems, its design is very important. In this paper we analyze the effect of thermal gradient on the clock distribution networks in the context of 3D ICs. We also propose novel methods for compensating the thermal effects which have been validated through extensive simulations and preliminary hardware measurements.

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“…However, those methods are either inefficient or not general enough even for 2D chips. The technique proposed by Shakeri and Meindl in [7] uses a temperature variable supply voltage (TVS) scheme where the supply voltage is adjusted around the ZTC point to nullify the thermally induced delay variation in the interconnects. The ZTC point occurs at a voltage around 0.37V for the 45nm node, which will greatly reduce the speed of circuit operations.…”

Section: Introductionmentioning

confidence: 99%

Expression of Concern: Thermally Robust Clocking Schemes for 3D Integrated Circuits

Mondal¹,

Ricketts²,

Kirolos³

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers. However, dissipating the heat generated in the 3D chips possesses a major challenge to the success of the technology and is the subject of active current research. Since the generated heat degrades the performance of the chip, thermally insensitive/adaptive circuit design techniques are required for better overall system performance. In this paper, we propose a thermally adaptive 3D clocking scheme that dynamically adjusts the driving strengths of the clock buffers to reduce the clock skew between terminals. We investigate the relative merits and demerits of two alternative clock tree topologies in this work. Simulation results demonstrate that our adaptive technique is capable of reducing the skew by 61.65% on the average, leading to much improved clock synchronization and design performance in the 3D realm.

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Temperature variable supply voltage for power reduction

Cited by 12 publications

References 6 publications

3-D Stacked Tier-Specific Microfluidic Cooling for Heterogeneous 3-D ICs

3-D Stacked Tier-Specific Microfluidic Cooling for Heterogeneous 3-D ICs

Timing analysis for thermally robust clock distribution network design for 3D ICs

Expression of Concern: Thermally Robust Clocking Schemes for 3D Integrated Circuits

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