Temperature-dependent field-effect measurements method to illustrate the relationship between negative bias illumination stress stability and density of states of InZnO-TFTs with different channel layer thickness

Huang, Chuan-Xin; Li, Jun; Ding, Xiaobin; Zhang, Jianhua; Jiang, Xue-Yin; Zhang, Zhilin

doi:10.1016/j.spmi.2015.02.043

Cited by 8 publications

(2 citation statements)

References 27 publications

(24 reference statements)

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“… here I D 0 , k , and T are the prefactor, Boltzmann constant, and the absolute temperature, respectively. 24 For the TFT using 10 nm-thick IGZO channel, the maximum E A was 0.76 eV at V GS of −1.8 V, which corresponded to the highest energy barrier for the trapped electrons. The maximum E A (1.31 eV) for the 6 nm-thick IGZO channel device was observed at V GS of −2.0 V. From these results, we estimated the decreasing rates of E A values to be 0.59 and 0.93 eV V −1 when the IGZO channel thickness was varied to 10 and 6 nm, respectively; these results are related to the density of states located in the band gap.…”

Section: Resultsmentioning

confidence: 90%

Investigations on the bias temperature stabilities of oxide thin film transistors using In–Ga–Zn–O channels prepared by atomic layer deposition

et al. 2018

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Bias temperature stress stabilities of thin-film transistors (TFTs) using In-Ga-Zn-O (IGZO) channels prepared by the atomic layer deposition process were investigated with varying channel thicknesses (10 and 6 nm). Even when the IGZO channel thickness was reduced to 6 nm, the device exhibited good characteristics with a high saturation mobility of 15.1 cm 2 V À1 s À1 and low sub-threshold swing of 0.12 V dec À1. Excellent positive and negative bias stress stabilities were also obtained. When positive bias temperature stress (PBTS) stability was tested from 40 to 80 C for 10 4 s, the threshold voltages (V TH ) of the device using the 6 nm-thick IGZO channel shifted negatively, and the V TH shifts increased from À0.5to À6.9 V with the increasing temperature. Time-dependent PBTS instabilities could be explained by a stretched-exponential equation, representing a charge-trapping mechanism.

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Section: Resultsmentioning

confidence: 90%

Investigations on the bias temperature stabilities of oxide thin film transistors using In–Ga–Zn–O channels prepared by atomic layer deposition

et al. 2018

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“…Figure shows that the activation energy depends on V GS for different channel layer thicknesses of a‐SZTO TFTs in the subthreshold region. The thermally activated drain current in the subthreshold region is given as

{normalI}_{normalD} {= I}_{D0} \cdot exp true(‐ \frac{{normalE}_{normala}}{kT} true)

where I D0 is the prefactor, k is the Boltzmann constant, and T is the absolute temperature. The slow falling rate indicates the increasing bulk and interface trap density .…”

Section: Resultsmentioning

confidence: 99%

Influence of Channel Layer Thickness on the Instability of Amorphous SiZnSnO Thin Film Transistors Under Negative Bias Temperature Stress

Lee

2018

Physica Status Solidi (a)

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In this study, amorphous silicon-zinc-tin-oxide thin film transistors (a-SZTO TFTs) are fabricated by radio-frequency magnetron sputtering at room temperature, and the influence of various channel thicknesses on their electrical performance and stability is report. Under the negative bias temperature stress, the transfer curve exhibits threshold voltage shift in the negative direction and degradation of subthreshold swing. In addition, the hump effect occurs in the thick channel, which is primarily due to an increase in total trap density from 5.0 Â 10 11 to 3.5 Â 10 12 cm À2 with an increase in the channel layer thickness from 12 to 72 nm. These results agree well with the increase in the bulk trap density because all a-SZTO TFTs have the same interface; therefore, the interface trap density is excluded. Thicker SZTO TFTs show the hump effect, as they have more donor-like states in the shallow level. Furthermore, temperature stress at 300-333 K and the activation energy (E a ) falling rate are calculated for a-SZTO TFTs. The E a falling rate decreases from 0.103 to 0.010 eV V À1 with increasing channel thickness. Consequently, an a-SZTO TFT with a 12-nm channel layer thickness shows a large E a falling rate (0.103 eV V À1 ) and a small threshold voltage shift of 4.74 V without the hump effect and degraded electrical performance.

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Device characteristics of amorphous ZnSnLiO thin film transistors with various channel layer thicknesses

Wang

Zhang

et al. 2016

Appl. Phys. A

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Temperature-dependent field-effect measurements method to illustrate the relationship between negative bias illumination stress stability and density of states of InZnO-TFTs with different channel layer thickness

Cited by 8 publications

References 27 publications

Investigations on the bias temperature stabilities of oxide thin film transistors using In–Ga–Zn–O channels prepared by atomic layer deposition

Investigations on the bias temperature stabilities of oxide thin film transistors using In–Ga–Zn–O channels prepared by atomic layer deposition

Influence of Channel Layer Thickness on the Instability of Amorphous SiZnSnO Thin Film Transistors Under Negative Bias Temperature Stress

Device characteristics of amorphous ZnSnLiO thin film transistors with various channel layer thicknesses

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