Temperature Dependence of Substrate and Drain–Currents in Bulk FinFETs

Kim, Sang-Yun; Kim, Young Min; Baek, Kwang-Ho; Choi, Byung−Kil; Han, Kyoung-Rok; Park, Ki-Heung; Lee, Jong-Ho

doi:10.1109/ted.2007.894605

Cited by 30 publications

(9 citation statements)

References 9 publications

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“…Some FinFET-based circuits based on 32nm PTM have shown the similar result when operating at superthreshold V dd [17]. Reference [18] analyzed this opposite temperature influence on I on , illustrating that this effect results from the bandgap narrowing and carrier mobility changes, which are induced by tensile stress effect of the insulator in the FinFET structure. As technology scales down (e.g., beyond 30nm), the tensile stress from the insulator layer to the fin body (cf.…”

Section: Temperature Effect Inversion (Tei) Phenomenon In Finfetsmentioning

confidence: 89%

Dynamic thermal management for FinFET-based circuits exploiting the temperature effect inversion phenomenon

Lee

Wang

Cui

et al. 2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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Due to limits on the availability of the energy source in many mobile user platforms (ranging from handheld devices to portable electronics to deeply embedded devices) and concerns about how much heat can effectively be removed from chips, minimizing the power consumption has become a primary driver for system-on-chip designers. Because of their superb characteristics, FinFETs have emerged as a promising replacement for planar CMOS devices in sub20nm CMOS technology nodes. However, based on extensive simulations, we have observed that the delay vs. temperature characteristics of FinFET-based circuits are fundamentally different from that of the conventional bulk CMOS circuits, i.e., the delay of a FinFET circuit decreases with increasing temperature even in the super-threshold supply voltage regime. Unfortunately, the leakage power dissipation of the FinFET-based circuits increases exponentially with the temperature. These two trends give rise to a tradeoff between delay and leakage power as a function of the chip temperature, and hence, lead to the definition of an optimum chip temperature operating point (i.e., one that balances concerns about the circuit speed and power efficiency.) This paper presents the results of our investigations into the aforesaid temperature effect inversion (TEI) and proposes a novel dynamic thermal management (DTM) algorithm, which exploits this phenomenon to minimize the energy consumption of FinFET-based circuits without any appreciable performance penalty. Experimental results demonstrate 40% energy saving (with no performance penalty) can be achieved by the proposed TEI-aware DTM approach compared to the best-inclass DTMs that are unaware of this phenomenon.

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Section: Temperature Effect Inversion (Tei) Phenomenon In Finfetsmentioning

confidence: 89%

Dynamic thermal management for FinFET-based circuits exploiting the temperature effect inversion phenomenon

Lee

Wang

Cui

et al. 2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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“…This clearly revealed that the improved HC resistance of narrow fin transistors is due to a lower carrier generation, i.e., a lower I B [42]. In addition, a better HC performance of narrow n-channel fins was found at higher temperatures (120 o C) [37].This temperature effect has been ascribed to the different thermal expansion of the SiN spacers compared with Si in Fig. 10, which exercise an increasing tensile stress on the fins.…”

Section: Reliabilitymentioning

confidence: 98%

“…The self-heating can be partly resolved by implementing socalled body-tied (BT) or bulk FinFETs [37,[42][43][44][45][46], represented in Fig. 10.…”

Section: Reliabilitymentioning

confidence: 99%

“…10, which exercise an increasing tensile stress on the fins. This stress is higher for narrower devices and results in a bandgap narrowing, which gives rise to a higher electron mobility, a lower threshold voltage (nFinFETs) and a better drain current [37]. No such impact was found for the p-channel transistors.…”

Section: Reliabilitymentioning

confidence: 99%

“…The S/D junction depth (x j ) is defined as a vertical depth from the top of the fin body. The thick arrow marks stand for the direction of the stress by the SiN expansion with increasing temperature[37]. (b) TEM photograph illustrating a bulk FinFET with high-κ dielectric and metal gate (courtesy A. Redolfi).…”

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confidence: 99%

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Reliability performance characterization of SOI FinFETs

Claeys

Put

Rafı́

et al. 2009

2009 2nd International Workshop on Electron Devices and Semiconductor Technology

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FinFET devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling CMOS to 22 nm and below. Some physical characterization and reliability aspects of these devices are reviewed. Attention is given to transient floating body effects and low frequency noise, which may yield information on the materials' characteristics like carrier recombination lifetime or interface and oxide trap density. These methods can be useful to study the performance of these components under harsh operation conditions of low or high temperature, or at high bias voltages.

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