Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections

Gaspard, N. J.; Jagannathan, S.; Diggins, Z. J.; King, Michael Patrick; Wen, S.-J.; Wong, Richard; Loveless, T. D.; Lilja, K.; Bounasser, M.; Reece, Trey; Witulski, A.F.; Holman, W.T.; Bhuva, B. L.; Massengill, L.W.

doi:10.1109/tns.2013.2289745

Cited by 41 publications

(15 citation statements)

References 17 publications

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“…Technology scaling has increased the vulnerability of flipflops to single-event upset (SEU) [1,2,3]. Reduced nodal capacitance and supply voltage decrease the critical charge required to upset [4,5,6,7].…”

Section: Introductionmentioning

confidence: 99%

MSIFF: A radiation-hardened flip-flop via interleaving master-slave stage layout topology

Song

Shao

Liang

et al. 2020

IEICE Electron. Express

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This paper presents a radiation-hardened flip-flop called MSIFF. The sensitive node-pairs between the master and slave latches are readjusted at layout-level. It obtains a high SEU tolerance with slight area and performance degradation. A test chip was irradiated with the static and dynamic test modes to validate the SEU tolerance of the proposed MSIFF. Experimental results demonstrate superior performance of the MSIFF over the conventional DICE and D flip-flop.

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Section: Introductionmentioning

confidence: 99%

MSIFF: A radiation-hardened flip-flop via interleaving master-slave stage layout topology

Song

Shao

Liang

et al. 2020

IEICE Electron. Express

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“…Single event transients (SETs) has become a major reliability concern for nanoscale technologies [1,2,3]. Reduced nodal capacitances and supply voltages decrease the minimal charge to cause a transient pulse [4,5,6,7].…”

Section: Introductionmentioning

confidence: 99%

“…The SET distributions for the target circuit C-E.IEICE Electronics Express, Vol.16, No.8,[1][2][3][4] …”

mentioning

confidence: 99%

Characterization of P-hit and N-hit single-event transient using heavy ion microbeam

Song

Shao

Liang

et al. 2019

IEICE Electron. Express

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P-hit and N-hit single-event transients are investigated using heavy ion microbeam. A novel layout placement was implemented in the test chip to distinguish SETs originating from P-hit and N-hit. Experimental results indicate both the P-hit and N-hit SETs show an exponentiallike distribution in all target circuits. The SET cross sections and the average pulse width for P-hit and N-hit are also investigated. The well process, the transistor size and the layout topology significantly impact on the cross sections. Only the transistor size impacts on the average pulse width at low LET.

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“…As technology progresses, some redundancy designs become sensitive, the single event upset (SEU) mitigation of DICE flip-flop decreases greatly compared with D flip-flop [9]. The difference between D and DICE flip-flop error rates decreases to about 30%-50% in 40 nm technology [10].…”

Section: Introductionmentioning

confidence: 99%

Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology

Huang

Chen

2016

Sci. China Inf. Sci.

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Single event upset (SEU) is one of the most important origins of soft errors in aerospace applications. As technology scales down persistently, charge sharing is playing a more and more significant effect on SEU of flip-flop. Charge sharing can often bring about multi-node charge collection in storage nodes and non-storage nodes in a flip-flop. In this paper, multi-node charge collection in flip-flop data input and flip-flop clock signal is investigated by 3D TCAD mixed-mode simulations, and the simulate results indicate that single event double transient (SEDT) in flip-flop data input and flip-flop clock signal can also cause a SEU in flip-flop. This novel mechanism is called the SEDT-induced SEU, and it is also verified by heavy-ion experiment in 65 nm twin-well process. The simulation results also indicate that this mechanism is closely related with the well-structure, and the triple-well structure is more effective to increase the SEU threshold of this mechanism than twin-well structure.Keywords single event upset (SEU), single event double transient (SEDT), SEDT-induced SEU, parasitic bipolar effect (PBE), charge sharing CitationHuang P C, Chen S M, Chen J J. Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology. Sci China Inf Sci,

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Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections

Cited by 41 publications

References 17 publications

MSIFF: A radiation-hardened flip-flop via interleaving master-slave stage layout topology

MSIFF: A radiation-hardened flip-flop via interleaving master-slave stage layout topology

Characterization of P-hit and N-hit single-event transient using heavy ion microbeam

Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology

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