Tarantula: a vector extension to the alpha architecture

Abstract

Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processor [6,5]. Tarantula adds to the EV8 core a vector unit capable of 32 double-precision flops per cycle. The vector unit fetches data directly from a 16 MByte second level cache with a peak bandwidth of sixty four 64-bit values per cycle. The whole chip is backed by a memory controller capable of delivering over 64 GBytes/s of raw bandwidth. Tarantula extends the Alpha ISA with new vector instructions that operate on new architectural state. Salient features of the architecture and implementation are: (1) it fully integrates into a virtual-memory cache-coherent system without changes to its coherency protocol, (2) provides high bandwidth for non-unit stride memory accesses, (3) supports gather/scatter instructions efficiently, (4) fully integrates with the EV8 core with a narrow, streamlined interface, rather than acting as a co-processor, (5) can achieve a peak of 104 operations per cycle, and (6) achieves excellent "real-computation" per transistor and per watt ratios. Our detailed simulations show that Tarantula achieves an average speedup of 5X over EV8, out of a peak speedup in terms of flops of 8X. Furthermore, performance on gather/scatter intensive benchmarks such as Radix Sort is also remarkable: a speedup of almost 3X over EV8 and 15 sustained operations per cycle. Several benchmarks exceed 20 operations per cycle.

A Case for a Flexible Scalar Unit in SIMT Architecture

“…GPGPU exploits the SIMT architecture, which is evolved from vector processors [9] Compared with previous studies on vector processors, the scalar unit and SIMT unit in our architecture are decoupled and have their own instruction streams. Such decoupled execution provides flexible ways to improve the performance as shown in our collaborative execution paradigms.…”

MVP-Cache: A Multi-Banked Cache Memory for Energy-Efficient Vector Processing of Multimedia Applications

“…Conventional multi-banked cache memories can be classified into the multi-banked cache memories with large cache lines (MBC-L) [11] and with small cache lines (MBC-S) [7]. In this paper, a multi-banked cache memory is classified into MBC-S if its cache line size is 8 bytes or smaller, otherwise it is classified into MBC-L.…”

“…The cache line size of this MBC-L is assumed to be 32 bytes. In this case, since each cache line can store four elements, the consecutive elements V[0] to V [3] are stored in sub-cache0, and elements V [4] to V [7] are stored in sub-cache1.…”

“…Moreover, to obtain a high cache bandwidth, a large number of sub-caches would be employed. Espasa et al [7] have proposed an MBC-L for a vector ISA extension. Their MBC-L adopts 16 sub-caches and the cache line size of each sub-cache is 64 bytes, which is the size of eight double-precision floating-point elements.…”

“…Espasa et al have proposed an out-of-order vector architecture [13] and have applied it to Tarantula [7], a vector extension to the Alpha processor. The cache mechanism of Tarantula, which is categorized into MBC-L, employs 16 sub-caches and an address re-ordering algorithm [14] to reduce the bank conflictions.…”