Tabular techniques for Reed—Muller logic

Almaini, A. E. A.; Thomson, Peter Frederic; Hanson, David R.

doi:10.1080/00207219108921253

Cited by 45 publications

(27 citation statements)

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“…However, methods to avoid the computation of all possible polarities similar to the ones introduced for GRMs [25,143] have to be developed to overcome the high computational complexity of MIKRM forms. Additionally, it has to be investigated which multiplevalued decoders are practical for circuit realizations.…”

Section: Ix6 Evaluanon and Resultsmentioning

confidence: 99%

“…Recently, there has been an increased interest in canonic forms over the Galois Field(2) [23][24][25][26]29,43,75,92]. One of the reasons to study such forms is that for each of the 2 n polarities they are canonical, which has several applications in both theory and practice.…”

Section: Multiple-valued Input Generalized Reed-muller Formsmentioning

confidence: 99%

“…The research on Exclusive Sum of Product (ESOP) fOnTIs, the counterpart to Sum of product (SOP) fOnTIS for AND, EXOR circuits, has been mainly concentrated on canonical Reed-Muller fOnTIS [14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31]. Because of their excellent design for testability [32][33][34][35][36][37] they have been, in spite of the fact that those fOnTIS mostly lead to non-minimal circuit realizations, an alternative design approach.…”

Section: Introductionmentioning

confidence: 99%

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Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping

Schäfer¹

2000

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The growing complexity of integrated circuits and the large variety of architectures of Field Programmable Gate Arrays (FPGAs) require sophi~ticated logic design tools. In 2 the beginning of the eighties the research in logic design was concentrated on the development of fast two-level AND-OR logic minimizers like the well known ESPRESSO. However, most logic functions have a smaller and often faster circuit realization as a multi-level circuit. Thus, synthesis tools emerged for the minimization of the circuit area in a multi-level realization. Most of these synthesis tools are based on the "unate paradigm". Therefore, the synthesis methods are only advantageous for functions having a minimal circuit realization based on AND-OR gates. However, many common functions have a minmal circuit realization having a mix of AND, OR and EXOR gates like counters, adders, multipliers, and parity generators. Therefore, the design of such functions with synthesis tools based on the "unated paradigm" is very inefficient Circuits incorporating the EXOR gate have received less attention than AND-OR circuits because the EXOR gate was perceived as slower and larger in terms of its circuit realization than the AND and the OR gate. However, the upcoming of Field Programmable Gate Arrays (FPGAs) like the Xilinx Table-Look-Up (TLU) architecture the Actel ACT™ series and the CLi 6000 series from Concurrent Logic, which allow the realization of the EXOR gate with the same speed and circuit cost as the AND and OR gate, eliminates the disadvantages of the EXOR gate over the AND and OR gate. Thus, there is a strong need for logic synthesis tools that take advantage of EXOR gates.The mapping to th~new FPGAs recently obtained an increased interest. The developed synthesis algorithms for FPGAs are based on the mapping and restructuring of the Directed Acyclic Graph (DAG) representation of the logic function. Even though the new FPGAs allow the realization of the EXOR gate without any speed and circuit size penalty in comparison to the AND and OR gate, the synthesis methods have been based on the "unate paradigm".To overcome the disadvantages of the current logic synthesis tools with respect to (nearly) linear functions and FPGA synthesis, this dissertation introduces an extended 3 theory of spectral methods for multiple-valued input, incompletely specified binary output logic. The spectral methods have not been popular in logic synthesis because of their four major drawbacks:(1) the computational complexity, especially if no Fast Transform exists, (2) the memory requirement to store the function in the necessary minterm representation, (3) they can not take efficiently advantage of incompletely specified functions, (4) suitable only for few applications in logic synthesis.To overcome the two last stated drawbacks, this dissertation introduces the T spectrum. The T spectrum separates the information obtained for the specified and not specified parts of the underlying function. Thus, it is possible to determine directly the contribution of the sp...

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Section: Ix6 Evaluanon and Resultsmentioning

confidence: 99%

Section: Multiple-valued Input Generalized Reed-muller Formsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping

Schäfer¹

2000

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“…The idea of employing a form of tabulation method in this regime is not new (Habib 1989, Helliwell and Perkowski 1988, Almaini et al 1991. Other attempts have operated with the minterm expansion of the function or the zero polarity Reed-Muller expansion, i.e.…”

Section: Introductionmentioning

confidence: 97%

“…These procedures can involve algebraic manipulations, maps or tabulation methods. There is a rapidly expanding literature relating to the design and simplification of switching circuits represented using the Reed-Muller algebraic techniques (Besslich 1983, Zhang and Rayner 1984, Green 1990, 1991, Lofti ef al. 1979, Kantapoulos 1980, Tran 1987, Bioul and Davio 1972, Habib 1989, Helliwell and Perkowski 1988, Almaini er al.…”

Section: Introductionmentioning

confidence: 99%

Tabular simplification method for switching functions expressed in Reed-Muller algebraic form

Green

Khuwaja

1993

International Journal of Electronics

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A tabulation method for the simplification of arbitrary modulo-2 sums-of-products expressions is described. The concept of the factorant is introduced and the means whereby the factorant structure of an expression can be determined is described. The simplified form is then expressed as an optimum sum of factorants which has the same truth vector as the original expression. The method avoids the use of large matrices or maps and is limited more by the number of product terns in the original expression than by the number of variables. The effectiveness of the procedure and modified versions of the basic algorithm are assessed by applying these to a large number of randomly generated expressions.

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