TAB barrier: Hybrid barrier synchronization for NoC-based processors

Wei, Zhenqi; Liu, Peilin; Sun, Rongdi; Ying, Rendong

doi:10.1109/iscas.2015.7168657

Cited by 7 publications

(6 citation statements)

References 11 publications

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“…Hardware-based barrier synchronization is implemented using a G-line based network allowing efficient signaling of barrier arrival and release [12]. A hybrid tree-based all-to-all barrier for NoC-based manycore system is explored in [2] to improve the performance by avoiding the off-centered barrier core. However, they are all based on multiple unicast packets, which is not efficient in parallel computing.…”

Section: Literature Reviewmentioning

confidence: 99%

“…Performance can be further improved over the works [2][9] by efficiently combining both wired and wireless infrastructures for broadcast as well as unicast operations. The main reason is that the access to WI is not guaranteed.…”

Section: B Dynamic Broadcast Mode Controllermentioning

confidence: 99%

“…In conventional NoC architectures support broadcast operations in the form of multiple unicast transmissions, which results in a significant increase of the latency and energy consumption of NoC. Recently, NoC architectures have been explored to address the challenges during barrier synchronization [1] [2], but these proposed solutions suffer from scalability issues. Emerging interconnect architectures aim to reduce performance by limiting multi-hop communication in conventional wired NoCs.…”

Section: Introductionmentioning

confidence: 99%

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Broadcast Mechanism Based on Hybrid Wireless/Wired NoC for Efficient Barrier Synchronization in Parallel Computing

Mondal

Chatterjee

Cataldo

et al. 2020

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Parallel computing is essential to achieve the manycore architecture performance potential, since it utilizes the parallel nature provided by the hardware for its computing. These applications will inevitably have to synchronize its parallel execution: for instance, broadcast operations for barrier synchronization. Conventional network-on-chip architectures for broadcast operations limit the performance as the synchronization is affected significantly due to the critical path communications that increase the network latency and degrade the performance drastically. A Wireless network-on-chip offers a promising solution to reduce the critical path communication bottlenecks of such conventional architectures by providing hardware broadcast support. We propose efficient barrier synchronization support using hybrid wireless/wired NoC to reduce the cost of broadcast operations. The proposed architecture reduces the barrier synchronization cost up to 42.79% regarding network latency and saves up to 42.65% communication energy consumption for a subset of applications from the PARSEC benchmark.

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Section: Literature Reviewmentioning

confidence: 99%

Section: B Dynamic Broadcast Mode Controllermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Broadcast Mechanism Based on Hybrid Wireless/Wired NoC for Efficient Barrier Synchronization in Parallel Computing

Mondal

Chatterjee

Cataldo

et al. 2020

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…A hardware-based barrier synchronization is implemented using G-line based network to allow for efficient signaling of barrier arrival and departure [3]. A hybrid treebased all-to-all barrier for NoC-based manycore system processors is explored in [5] to improve the performance by avoiding the off-centered barrier core. However, they are all based on multiple unicast packets, which is not efficient in parallel computing.…”

Section: Related Workmentioning

confidence: 99%

“…It increases with system size, which is not a feasible solution for scalable barrier synchronization. Many authors [3][4] [5] [6] [7] have proposed a hybrid tree-based all-to-all barrier for NoCbased system, which improves the performance by avoiding the off-centered barrier core when compared to a master-slave and tree barrier. The number of processing elements in a system is increasing rapidly, and this trend will undoubtedly continue into the future.…”

Section: Introductionmentioning

confidence: 99%

Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in Parallel Computing

Mondal¹,

Cataldo²,

Marcon³

et al. 2018

2018 31st IEEE International System-on-Chip Conference (SOCC)

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Efficient synchronization is one of the basic requirements of effective parallel computing. A key operation of the POSIX Thread standard (PThread) is barrier synchronization, where multiple threads block on a userspecified point of execution until all of them have reached it. Conventional architectures for broadcast operations limit the achievable performance benefits as synchronization is significantly affected due to critical path communications. This increases the network latency and degrades the performance dramatically. A Wireless Network-on-Chip (WiNoC) offers a promising solution to reduce the long distance/critical path communication bottlenecks of conventional architectures by augmenting them with single hop, long-range wireless links. In this paper, we propose a power-aware broadcast enabled WiNoC architecture to reduce the cost of broadcast operations for barrier-based applications. The proposed architecture reduces the barrier synchronization cost up to 43.97% regarding network latency under the PARSEC benchmarks. It also saves up to 80.49% idle-state power consumption in WIs for a 64-core system compared with the conventional WiNoC architecture without incurring significant overhead.

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