Systemc cosimulation and emulation of multiprocessor soc designs

Benini, Luca; Bertozzi, Davide; Bruni, D.; Drago, N.; Fummi, Franco; Poncino, Massimo

doi:10.1109/mc.2003.1193229

Cited by 100 publications

(58 citation statements)

References 9 publications

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“…Широкое использование специальных вычислитель-ных устройств и систем управления, микропроцессор-ных комплектов, а также больших интегральных схем (БИС) памяти как статического, так и динамического типов, привело к образованию функционально закон-ченных цифровых устройств самого разнообразного назначения [1,2]. В связи с тем, что частота работы та-ких цифровых устройств управления может доходить до нескольких гигагерц, это приводит к необходимо-сти более полной проверки их работоспособности еще на этапе проектирования [3,4].…”

Section: анализ литературных данных и постановка проблемыunclassified

Digital devices signal processing system based on K-valued differential calculus

Гладких¹,

Дмитриенко²,

Leonov³

2014

EEJET

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Section: анализ литературных данных и постановка проблемыunclassified

Digital devices signal processing system based on K-valued differential calculus

Гладких¹,

Дмитриенко²,

Leonov³

2014

EEJET

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“…In directed acyclic graphs (DAGs), nodes represent atomic operations as well as directed edge data dependences between operations. DAGs depict the dataflow of an application and can be applied at different levels of granularity, ranging from logic operators [69] to tasks [70], [71] or packet processing [72]. These depictions can be extended in DAGs with periods and deadlines, in which computation tasks are annotated with execution deadlines and periods.…”

Section: A Dataflow Models For the Representation And Co-design Of Amentioning

confidence: 99%

Algorithm/Architecture Co-Exploration of Visual Computing on Emergent Platforms: Overview and Future Prospects

Lee

Chen

Mattavelli

et al. 2009

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-Concurrently exploring both algorithmic and architectural optimizations is a new design paradigm. This survey paper addresses the latest research and future perspectives on the simultaneous development of video coding, processing, and computing algorithms with emerging platforms that have multiple cores and reconfigurable architecture. As the algorithms in forthcoming visual systems become increasingly complex, many applications must have different profiles with different levels of performance. Hence, with expectations that the visual experience in the future will become continuously better, it is critical that advanced platforms provide higher performance, better flexibility, and lower power consumption. To achieve these goals, algorithm and architecture co-design is significant for characterizing the algorithmic complexity used to optimize targeted architecture. This paper shows that seamless weaving of the development of previously autonomous visual computing algorithms and multicore or reconfigurable architectures will unavoidably become the leading trend in the future of video technology.

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“…For software, estimated elapsed time may be annotated in host code instead of using cycle accurate ISS. Similarly, Transaction Level Model (TLM) is popularly used with system-level design languages like SystemC [8]. However, cycle accurate system verification with ISS and RTL simulators is still preferred at the final stage of the system design in practice, since TLM does not provide enough timing accuracy for system verification.…”

Section: A Efficient System Timing Verificationmentioning

confidence: 99%

A timed HW/SW coemulation technique for fast yet accurate system verification

Yang

2009

2009 International Symposium on Systems, Architectures, Modeling, and Simulation

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-In System-on-chip (SoC) design, it is essential to verify the correctness of design before a chip is fabricated. While conventional hardware emulators validate functional correctness of hardware components quickly, only a few researches exist to use hardware emulators for timing verification since synchronization between the hardware emulator and the other parts easily overwhelms the gain of hardware emulator. In this paper we propose a novel hardware/software coemulation framework for fast yet accurate system verification based on the virtual synchronization technique. For virtual synchronization, interface protocol and interface logic between a hardware emulator and the HW/SW coemulation kernel are proposed. Experiments with real-life examples prove the effectiveness of the proposed technique.

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Systemc cosimulation and emulation of multiprocessor soc designs

Cited by 100 publications

References 9 publications

Digital devices signal processing system based on K-valued differential calculus

Digital devices signal processing system based on K-valued differential calculus

Algorithm/Architecture Co-Exploration of Visual Computing on Emergent Platforms: Overview and Future Prospects

A timed HW/SW coemulation technique for fast yet accurate system verification

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