Systematic Hysteresis Analysis for Dynamic Comparators

Abstract

Comparator hysteresis is a memory phenomenon allowing outputs maintaining their past stable states until the input difference overcomes a given threshold voltage. In some applications, such as ADCs and memories, hysteresis is a deterministic error that should be minimized. In others, it can be considered as one of the design parameters, such as in implementing hysteresis control-based systems such as peak detectors and spectrum analyzers. In any case, the designer should be aware of how to estimate hysteresis to achieve the desired performances. This paper presents a mathematical approach to estimate hysteresis in clocked latch comparators. It has been demonstrated that hysteresis is not only sensitive to the clock frequency, but also to several design parameters including the transistors sizes, the common mode input voltage and the tracked input frequencies. The analysis results are validated through electrical simulations using a commercially available 0.18[Formula: see text][Formula: see text]m CMOS technology showing a maximum error of 8.6%.

Low-power latch comparator with accurate hysteresis control

“…Proposed latch comparator for hysteresis control with an analog adjustment voltage V Ad sis voltage V HY is then equal to the difference between trip points V TR + and V TR − . The reset and decision phases, including the regeneration process, were discussed in depth in [6]. Also, a thorough analysis of the circuit operating in both reset and decision phases, led to define hysteresis in terms of internal capacitors and initial voltage levels.…”

“…The initial voltages at nodes X 1−2 and O 1−2 will be denoted by V 0X1,2 and V 0O1,2 , respectively. The hysteresis voltage V HY is then a function of the initial voltage differences ∆V 0X = V 0X1 − V 0X2 and ∆V 0O = V 0O1 − V 0O2 and may be written as [6] V…”

“…As a result, speed optimization can be achieved by simply minimizing the devices' dimensions which also optimizes the power consumption and the silicon area. However, the circuit analysis must consider parasitics which increases the complexity of analytical developments [6]. The latter are crucial to achieve optimal performance, especially in dynamic circuits.…”

“…Recent works allowed defining hysteresis in dynamic comparators [6]. This circuit property is a prime characteristic of Schmitt triggers (STs) and is usually set to appropriate values to achieve a desired function.…”

Design optimisation procedure for digital mismatch compensation in latch comparators

“…It can be noted that the reset phase of the second stage is very brief and should begin slightly before starting a new decision phase. This allows setting both v O1,2 ′ to 0 V before the primary clock clk turns high in order to avoid increasing the comparator hysteresis [21]. Slightly after clk turns high, clk_2 goes low turning transistors ( M 7,8 ) off.…”