2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture 2010
DOI: 10.1109/micro.2010.26
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Abstract: Translation Look-aside Buffers (TLBs) are vital hardware support for virtual memory management in high performance computer systems and have a momentous influence on overall system performance. Numerous techniques to reduce TLB miss latencies including the impact of TLB size, associativity, multilevel hierarchies, super pages, and prefetching have been well studied in the context of uniprocessors. However, with Chip Multiprocessors (CMPs) becoming the standard design point of processor architectures, it is imp… Show more

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Cited by 57 publications
(32 citation statements)
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References 32 publications
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“…This mechanism, although simpler, has some similarities with the Synergistic TLBs mechanism proposed in [22]. Upon a TLB miss, getting the page information from a remote TLB is faster than from the page table, since "walking" the page table, often broken down into several levels, may imply several memory references (e.g., four memory references for the current 48-bit x86-64 virtual address space [23], or up to fifteen memory accesses for recent 32-bit ARMv7 virtual address space [24]).…”
Section: Tlb Miss Resolution Through Tlb-to-tlb Transferssupporting
confidence: 56%
See 1 more Smart Citation
“…This mechanism, although simpler, has some similarities with the Synergistic TLBs mechanism proposed in [22]. Upon a TLB miss, getting the page information from a remote TLB is faster than from the page table, since "walking" the page table, often broken down into several levels, may imply several memory references (e.g., four memory references for the current 48-bit x86-64 virtual address space [23], or up to fifteen memory accesses for recent 32-bit ARMv7 virtual address space [24]).…”
Section: Tlb Miss Resolution Through Tlb-to-tlb Transferssupporting
confidence: 56%
“…Concerning fast resolution of TLB misses, Synergistic TLBs [22] employs the snooping of other TLBs to propose a distributed-shared TLB organization. Also, UNITD Coherence [41] employs the TLB snooping to integrate the existing cache coherence protocol with the TLB coherence maintenance.…”
Section: Related Workmentioning
confidence: 99%
“…Efficient TLB mechanisms: Prior efforts improved TLB performance either by increasing the TLB hit rate or reducing/hiding the miss latency. For example, recent proposals increase the effective TLB size through co-operative caching of TLB entries [42] or a larger second-level TLB shared by multiple cores [7]. Prefetching was also proposed to hide the TLB miss latency [6,17,22].…”
Section: Related Workmentioning
confidence: 99%
“…TLBto-TLB transfers are based upon the observation that core-to-core communication in CMPs is much faster compared to traditional processors. Other works also benefit from this observation with different aims [63,81]. Snooping TLB-based classification targets purely-private, single or multilevel TLB structures.…”
Section: Snooping Tlb-based Classificationmentioning
confidence: 93%
“…Srikantaiah et al [81] observed that some applications show significant miss reduction when increasing the number of TLB entries (i.e., borrower ), whereas others' miss rate reduction is negligible (i.e., donor ). Moreover, duplicate translations in different TLBs waste TLB capacity.…”
Section: Inter-core Sharing Patternsmentioning
confidence: 99%