SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects

Postman, Jacob; Krishna, Tushar; Edmonds, Christopher; Peh, Li-Shiuan; Chiang, Patrick

doi:10.1109/tvlsi.2012.2211904

Cited by 28 publications

(12 citation statements)

References 26 publications

(69 reference statements)

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“…As a baseline, we also compare our proposed design with a conventional hop-by-hop routing approach. In particular, we assume a 1-cycle router with a single-cycle link traversal as this is the state-of-the-art in conventional hop-by-hop routing [19]. We refer to this approach as "Baseline."…”

Section: Performance Comparisonsmentioning

confidence: 99%

Smart-Hop Arbitration Request Propagation

Asgarieh

Lin

2019

ACM Trans. Des. Autom. Electron. Syst.

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SMART-based NoC designs achieve ultra-low latencies by enabling flits to traverse multiple hops within a single clock cycle. Notwithstanding the clear performance benefits, SMART-based NoCs suffer from several shortcomings: each router must arbitrate among a quadratic number of requests, which leads to high costs; each router independently makes its own arbitration decisions, which leads to a problem called false negatives that causes throughput loss. In this article, we propose a new SMART-based NoC design called SHARP that overcomes these shortcomings. Our evaluation demonstrates that SHARP increases throughput by up to 19% and average link utilization by up to 24% by avoiding false negatives. By avoiding quadratic arbitration, our evaluation further demonstrates that SHARP reduces the wiring and area overhead significantly.

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Section: Performance Comparisonsmentioning

confidence: 99%

Smart-Hop Arbitration Request Propagation

Asgarieh

Lin

2019

ACM Trans. Des. Autom. Electron. Syst.

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“…An effective way to reduce power consumption is reducing the number of pipeline stages that packets traverse to reach their destination. By reducing the pipeline stages, dynamic power is reduced as well reducing the workload latency [56,57].…”

Section: Reducing Power Consumption In the Noc Router Architecturementioning

confidence: 99%

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Ofori-Attah¹,

Wang²,

Agyeman³

2018

EAI Endorsed Transactions on Industrial Networks and Intelligen

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Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with manycore integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials.

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“…The following authors propose effective techniques for bypassing the buffering stage in one stage. Postman et al [80] proposes a Low-Power Network-on-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects (SWIFT) NoC, while Shenbagavelli [81] introduces virtual switching. The SWIFT NoC allows flits to pass through the buffering stage in a lesser number of cycles (one); ignoring the use of read/write power.…”

Section: Pipeline Stagesmentioning

confidence: 99%

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

Ofori-Attah

Bhebhe

Agyeman

2017

JLPEA

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The disparity between memory and CPU have been ameliorated by the introduction of Network-on-Chip-based Chip-Multiprocessors (NoC-based CMPS). However, power consumption continues to be an aggressive stumbling block halting the progress of technology. Miniaturized transistors invoke many-core integration at the cost of high power consumption caused by the components in NoC-based CMPs; particularly caches and routers. If NoC-based CMPs are to be standardised as the future of technology design, it is imperative that the power demands of its components are optimized. Much research effort has been put into finding techniques that can improve the power efficiency for both cache and router architectures. This work presents a survey of power-saving techniques for efficient NoC designs with a focus on the cache and router components, such as the buffer and crossbar. Nonetheless, the aim of this work is to compile a quick reference guide of power-saving techniques for engineers and researchers.

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SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects

Cited by 28 publications

References 26 publications

Smart-Hop Arbitration Request Propagation

Smart-Hop Arbitration Request Propagation

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

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