Study of Trap Models Related to the Variable Retention Time Phenomenon in DRAM

Kim, Heesang; Oh, Byoungchan; Son, Younghwan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Seongin; Shin, Hyungcheol

doi:10.1109/ted.2011.2125964

Cited by 11 publications

(3 citation statements)

References 14 publications

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“…These works established the key properties of VRT: the existence of multiple retention time states in VRT cells and the exponentially-distributed nature of the amount of time spent in each state. Since then, interest in VRT has focused on identifying its physical cause, primarily by measuring circuit-level features such as leakage currents [3,14,15,16,25,27,29]. No recent work we are aware of has evaluated the impact of VRT in modern DRAM devices.…”

Section: Variable Retention Timementioning

confidence: 99%

An experimental study of data retention behavior in modern DRAM devices

LiuJamie

JaiyenBen

KimYoongu

et al. 2013

SIGARCH Comput. Archit. News

176

403

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DRAM cells store data in the form of charge on a capacitor. This charge leaks off over time, eventually causing data to be lost. To prevent this data loss from occurring, DRAM cells must be periodically refreshed. Unfortunately, DRAM refresh operations waste energy and also degrade system performance by interfering with memory requests. These problems are expected to worsen as DRAM density increases.The amount of time that a DRAM cell can safely retain data without being refreshed is called the cell's retention time. In current systems, all DRAM cells are refreshed at the rate required to guarantee the integrity of the cell with the shortest retention time, resulting in unnecessary refreshes for cells with longer retention times. Prior work has proposed to reduce unnecessary refreshes by exploiting differences in retention time among DRAM cells; however, such mechanisms require knowledge of each cell's retention time.In this paper, we present a comprehensive quantitative study of retention behavior in modern DRAMs. Using a temperaturecontrolled FPGA-based testing platform, we collect retention time information from 248 commodity DDR3 DRAM chips from five major DRAM vendors. We observe two significant phenomena: data pattern dependence, where the retention time of each DRAM cell is significantly affected by the data stored in other DRAM cells, and variable retention time, where the retention time of some DRAM cells changes unpredictably over time. We discuss possible physical explanations for these phenomena, how their magnitude may be affected by DRAM technology scaling, and their ramifications for DRAM retention time profiling mechanisms.

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Section: Variable Retention Timementioning

confidence: 99%

An experimental study of data retention behavior in modern DRAM devices

LiuJamie

JaiyenBen

KimYoongu

et al. 2013

SIGARCH Comput. Archit. News

176

403

View full text Add to dashboard Cite

show abstract

“…ror models 4 ⃝ based on a previous understanding of DRAM errors (e.g., from past experiments or scientific studies). Examples of such error models include: analytical models based on understanding DRAM failure modes (e.g., sources of runtime faults [51,60,149,[371][372][373]), parametric statistical models that provide useful summary statistics (e.g., lognormal distribution of cell data-retention times [276,277,[374][375][376][377][378][379][380], exponential distribution of the time-in-state of cells susceptible to variable-retention time (VRT) [65,94,150,166,367,[381][382][383][384][385][386][387][388][389]), physics-based simulation models (e.g., TCAD [232,374,[390][391][392] and SPICE models [14,59,78,106,109,283,[393][394][395]), and empirically-determined curves that predict observations well (e.g., single-bit error rates…”

Section: Testing Modelingmentioning

confidence: 99%

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today's DRAM technology scaling challenges requires new solutions driven by both DRAM producers and consumers. In this paper, we observe that the separation of concerns between producers and consumers specified by industry-wide DRAM standards is becoming a liability to progress in addressing scaling-related concerns.To understand the problem, we study four key directions for overcoming DRAM scaling challenges using system-memory cooperation: (i) improving memory access latencies; (ii) reducing DRAM refresh overheads; (iii) securely defending against the RowHammer vulnerability; and (iv) addressing worsening memory errors. We find that the single most important barrier to advancement in all four cases is the consumer's lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, we recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, we propose adopting this revision in a two-step plan, starting with immediate information release through crowdsourcing and publication and culminating in widespread modifications to DRAM standards.

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“…Thermal generation occurs via the fast state. 7) The trap-assisted tunneling (TAT) current of p-n junction can be described based on the field enhancement factor Γ(F ) as follows: 8,9) I ¼…”

Section: Introductionmentioning

confidence: 99%

Analysis on the variable junction leakage in MOS transistors due to interaction between two traps

Shin

Jeon

Kim

et al. 2015

Jpn. J. Appl. Phys.

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In this paper, we analyzed the amplitude of variable junction leakage currents caused by the interaction between two interface states in MOS transistors. For the first time, an analytical equation for the ratio between the junction leakage current before and after electron capture into the slow state was derived with consideration of both the change in the capture cross-section and the electric field. Also, the correct equation for the electric field after electron trapping was derived and used. The distance between the two interface states was extracted from the equation and measurement data.

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Study of Trap Models Related to the Variable Retention Time Phenomenon in DRAM

Cited by 11 publications

References 14 publications

An experimental study of data retention behavior in modern DRAM devices

An experimental study of data retention behavior in modern DRAM devices

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Analysis on the variable junction leakage in MOS transistors due to interaction between two traps

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