Stress modeling of Cu/low-k BEoL - application to stress migration

Interface Reliability Assessments for Copper/Low-k Products

“…This new interconnect architecture has been found to possess certain vulnerabilities to voiding under electromigration stress in and around its Cu vias [32], [33]. Similar vulnerabilities to voiding have been found under thermomechanical stress [28], [34]- [47]. So far, the discussion of voiding in Cu-based interconnects has been solely attributed to the region in and around a Cu via and will be the focus of the rest of this discussion.…”

“…In the case of a nonrecessed via bottom, finite element analysis (FEA) favors a vacancy clustering process rather than a stress nucleation process [28]. Other FEA work has found that a region of higher tensile stress is present in the same region for a similar nominal geometry and would then implicate a stress nucleation event as the trigger for void growth [43], [47]. Such an interpretation would be more consistent with the stress migration picture developed for Al metallization.…”

“…Thus, use of materials with low coefficient of thermal expansion (CTE) mismatch to Cu would seem to be preferable to improve stress migration resistance, although materials choices may also be limited by other demands such as electrical leakage, hermeticity and package stress robustness. This impact might be negated, however, with the use of low-k dielectrics because they may allow Cu to void more readily [47]. Another important strategy is lessening the vacancy content within the metal.…”

Finite element analysis of thermal stress for different Cu interconnects structure

“…In order to reduce the hydrostatic stress in Cu lines and via, in this work, we study the effect of stress control layer (SCL), which is introduced between the low-k dielectric, on thermal stresses of Cu/low-k interconnects. Despite several studies in the literature, the thermal stress of Cu interconnects with gouging via is seldom reported [1,2]. However, via gouges into underlying metal lead during conventional Cu interconnects fabrication process is inevitable due to over-etching and cleaning at via bottom [3].…”

Impact of via interactions and metal slotting on stress induced voiding

“…In dual-damascene technology, the combined effects of the absence of a conductive shunt layer at the via-bottom/Cu/SiC intersection, the high Cu diffusivity path at the SiC/Cu interface, stress gradients under the via [5], and a small critical void volume for failure [6], can enable voids to nucleate below the via and easily grow to a fatal size. When identical test structures are serially connected, the timeto-failure (TTF) is driven by the earliest failure mode and the TTF distribution is known to follow "weakest-link" statistics [7].…”