Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques

Taraschi, Gianni; Pitera, Arthur J.; Fitzgerald, Eugene A.

doi:10.1016/j.sse.2004.01.012

Cited by 136 publications

(79 citation statements)

References 36 publications

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“…• C under a supply power density of 1000 W/cm 2 , whereas the temperature increase in SiO 2 bonded samples are 3.89 ± 0.10 and 3.56 ± 0.10 • C, respectively. As compared to the traditional bonding material SiO 2 , there is around 23% improvement in heat dissipation capability by using AlN as the bonding layer.…”

Section: Resultsmentioning

confidence: 94%

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AlN-AlN Layer Bonding and Its Thermal Characteristics

Bao

Lee

Chong

et al. 2015

ECS J. Solid State Sci. Technol.

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Homogeneous bonding was successfully demonstrated on 150 mm Si wafers by face-to-face direct dielectric bonding of clean and smooth aluminum nitride (AlN) layers. Characterization result from XPS confirms the layer composition and reveals that approximately 5 nm of the layer surface was partially oxidized during processing. After activation, substoichiometric nitrogen bound to aluminum, Al-O and Al-OH bonds were found at the thin film surface. The as-bonded wafer pairs are nearly void and particle free with a high bonding strength of 1527.8 ± 272.2 mJ/m 2 , enabling them to withstand the subsequent process steps. In addition, experimental results have indicated that the AlN-AlN bonded wafers can achieve a 23 and 16% improvement respectively in terms of heat dissipation compared with those using SiO 2 and Al 2 O 3 as the bonding layer. It is concluded that this AlN-AlN bonded wafer pairs can exhibit a better heat dissipation capability than other bonded counterparts. Wafer bonding allows heterogeneous integration of two materials that have similar or very different lattice parameters and thermal properties, via an intermediate bonding layer or direct bonding. One of the most prominent applications of wafer bonding is silicon-oninsulator (SOI), [1][2][3][4][5] and it can also be extended to germanium-oninsulator (GOI) 6,7 or other III-V groups integration. 8,9 First direct bonded SOI was reported by Lasky et al. in 1986. Since then, SOI fabricated from wafer bonding has been gaining ground from the conventional Si substrate in ultra-large scale integrations (ULSI) and micro-electro-mechanical systems (MEMS) 10 as the starting substrate, which benefits from its on-insulator structure. The "on-insulator" advantages make it possible to attain mechanical stability close to Si substrate and excellent electrostatic control, such as attenuated shortchannel effects, 11 reduced parasitic capacitance and absence of latchup. 12 As the most common buried insulator material, SiO 2 has already shown extensive popularity in a couple of optical devices. [13][14][15] However, the low thermal conductivity of SiO 2 (1.46 Wm −1 K −1 ) limits the heat dissipation efficiency and degrades the advantages of SOI. Also, the degraded heat dissipation path deteriorates its heat transfer efficiency to the underlying bulk Si layer, leading to severe self-heating effect. This effect is further magnified by device scaling for performance improvement, which constrains the applicability of SOI in electronics, especially in the cases where high temperature and power dissipation are expected. In order to address this problem, numerous efforts have been dedicated to exploring for novel buried insulator materials with high thermal conductivity such as diamond and silicon carbide. 16 Liang et al. had demonstrated the outstanding heat dissipation advantage of silicon-on-diamond (SOD) comparing to the conventional SOI substrate.17 Furthermore, high-k dielectric materials with high thermal conductivity have drawn great attention in SOI fabrication. For ...

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Section: Resultsmentioning

confidence: 94%

“…One of the most prominent applications of wafer bonding is silicon-oninsulator (SOI), [1][2][3][4][5] and it can also be extended to germanium-oninsulator (GOI) 6,7 or other III-V groups integration. 8,9 First direct bonded SOI was reported by Lasky et al in 1986.…”

mentioning

confidence: 99%

AlN-AlN Layer Bonding and Its Thermal Characteristics

Bao

Lee

Chong

et al. 2015

ECS J. Solid State Sci. Technol.

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“…Though some promise for creating "pure" Ge-on-insulator exists, either through wafer bonding [52] or novel epitaxial techniques [53], using the current direct Ge growth process, a minimum SOI layer thickness of ∼10 nm would probably need to be maintained. Also, in order to realize speed improvements by correspondingly reducing the finger spacing and Ge layer thickness, the RC-limited delay time would have to be reduced.…”

Section: B Outlook For Improved Performancementioning

confidence: 99%

Germanium-on-SOI Infrared Detectors for Integrated Photonic Applications

Koester

Schaub²,

Dehlinger

et al. 2006

IEEE J. Select. Topics Quantum Electron.

145

115

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Abstract-An overview of recent results on high-speed germanium-on-silicon-on-insulator (Ge-on-SOI) photodetectors and their prospects for integrated optical interconnect applications are presented. The optical properties of Ge and SiGe alloys are described and a review of previous research on SOI and SiGe detectors is provided as a motivation for the Ge-on-SOI detector approach. The photodetector design is described, which consists of lateral alternating p-and n-type surface contacts on an epitaxial Ge absorbing layer grown on an ultrathin-SOI substrate. When operated at a bias voltage of −0.5 V, 10 µm ×10 µm devices have dark current I dark , of only ∼10 nA, a value that is nearly independent of finger spacing S, between S = 0.3 µm and 1.3 µm. Detectors with S = 1.3 µm have external quantum efficiencies η, of 52% (38%) at λ = 895 nm (850 nm) with corresponding responsivities of 0.38 A/W (0.26 A/W). The wavelength-dependence of η agrees fairly well with expectations, except at longer wavelengths, where Si up-diffusion into the Ge absorbing layer reduces the efficiency. Detectors with 10 µm ×10 µm area and S = 0.6 µm have −3-dB bandwidths as high as 29 GHz, and can simultaneously achieve a bandwidth of 27 GHz with I dark = 24 nA, at a bias of only −1 V, while maintaining high efficiency of η = 46%(33%), at λ = 895 nm (850 nm). Analysis of the finger spacing and areadependence of the device speed indicates that the performance at large finger spacing is transit-time-limited, while at small finger spacing, RC delays limit the bandwidth. Methods to improve the device performance are presented, and it is shown that significant improvement in the speed and efficiency both at λ = 850 and 1300 nm can be expected by optimizing the layer structure design.

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“…A number of methods have been proposed to produce blanket SGOI films on Si wafers, including layer transfer [1,2] and Ge condensation [2,3]. A complementary technique to fabricate localized SGOI regions on a Si wafer is rapid melt growth (RMG) in micro-crucibles [4].…”

Section: Introductionmentioning

confidence: 99%