Stochastic modeling and performance evaluation for digital clock and data recovery circuits

Demіr, Alper; Feldmann, P.

doi:10.1145/343647.343793

Cited by 2 publications

(2 citation statements)

References 7 publications

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“…Nevertheless, the coarse problems retain enough characteristics of the fine problem so as to help accelerate the convergence. We implemented such a multi-level algorithm in [6], where the lumping and expanding steps are interleaved with simple Gauss-Jacobi iterations and the coarsest problem is solved exactly with a direct method. In this implementation [6], we use flat sparse storage for both the fine and the coarse problems and this severely limits the size of the problem that can be handled.…”

Section: Methodsmentioning

confidence: 99%

“…We implemented such a multi-level algorithm in [6], where the lumping and expanding steps are interleaved with simple Gauss-Jacobi iterations and the coarsest problem is solved exactly with a direct method. In this implementation [6], we use flat sparse storage for both the fine and the coarse problems and this severely limits the size of the problem that can be handled. In order to overcome this limitation, we introduce a novel, graph based, data structure capable of modeling systems with state spaces larger by about two orders of magnitude.…”

Section: Methodsmentioning

confidence: 99%

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Modeling and analysis of communication circuit performance using Markov chains and efficient graph representations

Demir¹,

Feldmann²

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH3714

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In high-speed data networks, the bit-error-rate specification on the system can be very stringent, i.e., 10¢ 14. At such error rates, it is not feasible to evaluate the performance of a design using straightforward, simulation based, approaches. Nevertheless performance prediction before actual hardware is built is essential for the design process. This work introduces a stochastic model and an analysis-based, non-Monte-Carlo method for performance evaluation of digital data communication circuits. The analyzed circuit is modeled by a number of interacting finite state machines with inputs described as functions on a Markov chain state-space. The composition of these elements results in a typically very large Markov chain. System performance measures, such as probability of bit errors and rate of synchronization loss, can be evaluated by solving linear problems involving the large Markov chain's transition probability matrix. This paper first describes a dedicated multi-grid method used to solve these very large linear problems. The principal bottleneck in such an approach is the size of the Markov chain state-space, which grows exponentially with system complexity. The second part of this paper introduces a novel, graph based, data structure capable of efficiently storing and manipulating transition probability matrices for several million state Markov chains. The methods are illustrated on a real industrial clock-recovery circuit design. 1 Introduction High-speed communication systems have extremely tight bit-error-rate (BER) specifications. For SONET/SDH applications it is not uncommon to have BER requirements in the order of 10£ 14. Such specifications are practically impossible to verify through straightforward simulation because of the extremely long sequence that would need to be simulated in order to get meaningful error statistics. In the absence of a performance analysis tool, designers rely on the experience of previous designs, intuition, and good luck. This environment discourages innovative solutions and non-incremental applications. On the other hand, the design process of communication systems would benefit significantly from the existence of a reliable design performance evaluation capability. Such a capability would permit the evaluation of a number of alternative algorithms, architectures, circuit techniques, and technologies in a short time and without the commitment of expensive resources. A situation that illustrates the need for a reliable evaluation capability of the BER occurred in the design of a SONET-type application at a well-known microelectronics company. The specification for a mul-tiplexer chip required a BER of 10£ 14. The prototype implementation, based on the modification of an existing design delivered performance that was more than an order of magnitude bellow the specification. The designers suspected that the main cause for the errors is the interference noise in the PLL-based clock recovery circuit, induced by the rest of the chip's circuitry. A number of circuit, technol...

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Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Modeling and analysis of communication circuit performance using Markov chains and efficient graph representations

Demir¹,

Feldmann²

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH3714

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A Noise Aware CML Latch Modelling for Large System Simulation

Bhatta

Bannerjee

Chatterjee

2015

2015 28th International Conference on VLSI Design

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Modern high speed communication systems often employ both analog and digital blocks. This poses a challenge for simulation of closed loop system dynamics in presence of non-idealities in any of the analog blocks. Due to the size and complexity of such systems it is not possible to do full system level simulation with circuit level models. The presence of digital control blocks makes it difficult to elevate block level observations to system level performance. A major challenge is the difficulty in estimating the error rate at the output of digital latches (continuous-time to discrete-time domain crossing boundaries) in the presence of noise and non-ideal analog input signals. Simplistic models used currently are often inadequate in capturing the long term effects of non ideal behavior at the block level. In this paper we propose a simulation framework to estimate latch transition probabilities in the response to distorted input and clock waveforms in presence of white noise. The evaluated transition probabilities can then be used to estimate system performance in an event driven Markov chain based model.

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Stochastic modeling and performance evaluation for digital clock and data recovery circuits

Cited by 2 publications

References 7 publications

Modeling and analysis of communication circuit performance using Markov chains and efficient graph representations

Modeling and analysis of communication circuit performance using Markov chains and efficient graph representations

A Noise Aware CML Latch Modelling for Large System Simulation

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