Statistical Analysis of Soft Error Rate in Digital Logic Design Including Process Variations

Yao, Jian; Ye, Zuochang; Li, Miao; Li, Yanfeng; Schrimpf, R.D.; Fleetwood, D.M.; Wang, Yan

doi:10.1109/tns.2012.2219070

Cited by 10 publications

(2 citation statements)

References 19 publications

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“…One is the incidence rates of SEU and SET themselves, and the other is the area ratio of circuit elements which induce transient and persistent errors. The former is analyzed and measured in previous works [15], [16], so that the soft-error rates in flipflops and combinational circuits can be regarded to have the equivalent order of magnitude in the advanced process technologies. Therefore, in reconfigurable arrays, such as FPGA and CGRA, the area of the configuration memory and that of the acyclic data path defines the ratio between persistent and transient errors, respectively.…”

Section: Soft Errormentioning

confidence: 99%

An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs

Imagawa

Hiromoto

Ochi

et al. 2015

IEICE Trans. Electron.

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Time redundancy is sometimes an only option for enhancing circuit reliability when the circuit area is severely restricted. In this paper, a time-redundant error-correction scheme, which is particularly suitable for coarse-grained reconfigurable arrays (CGRAs), is proposed. It judges the correctness of the executions by comparing the results of two identical runs. Once a mismatch is found, the second run is terminated immediately to start the third run, under the assumption that the errors tend to persist in many applications, for selecting the correct result in the three runs. The circuit area and reliability of the proposed method is compared with a straightforward implementation of time-redundancy and a selective triple modular redundancy (TMR). A case study on a CGRA revealed that the area of the proposed method is 1% larger than that of the implementation for the selective TMR. The study also shows the proposed scheme is up to 2.6x more reliable than the full-TMR when the persistent error is predominant.

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Section: Soft Errormentioning

confidence: 99%

An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs

Imagawa

Hiromoto

Ochi

et al. 2015

IEICE Trans. Electron.

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“…), it provides an estimate of the soft error susceptibility, and can be used to further estimate the SER [7]. Recent works estimate from simulations that SER variation in digital logic blocks will scale from around 30% in 90 nm CMOS technologies up to 120% for the 28nm CMOS technology node [8]. Such SER variation is also expected to occur in memory circuits where devices are typically minimum sized and therefore highly subjected to process parameter variations.…”

Section: Introductionmentioning

confidence: 99%

SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results

Torrens

Paul

Alorda

et al. 2014

IEEE Trans. Nucl. Sci.

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Experimental results from a 65nm CMOS commercial technology SRAM test chip reveal a linear correlation between a new electrical parameter -the word-line voltage margin (V WLVM )-and the measured circuit alpha-SER.Additional experiments show that no other memory cell electrical robustness-related parameters exhibit such correlation. The technique proposed is based on correlating the V WLVM to the SER measured on a small number of circuit samples to determine the correlation parameters. Then, the remaining non-irradiated circuits SER is determined from electrical measurements (V WLVM ) without the need of additional radiation experiments. This method represents a significant improvement in time and cost, while simplifying the SER-determination methods since most of the circuits do not require irradiation. The technique involves a minor memory design modification that does not degrade circuit performance, while circuit area increase is negligible.

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Line-edge roughness induced single event transient variation in SOI FinFETs

Jiang

et al. 2015

J. Semicond.

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The impact of process induced variation on the response of SOI FinFET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When FinFET biased at OFF state configuration (V gs D 0, V ds D V dd / is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse (single event transient, SET) is consequently formed. The results reveal that with the presence of line-edge roughness (LER), which is one of the major variation sources in nano-scale FinFETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered: type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters, correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size.

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Statistical Analysis of Soft Error Rate in Digital Logic Design Including Process Variations

Cited by 10 publications

References 19 publications

An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs

An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs

SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results

Line-edge roughness induced single event transient variation in SOI FinFETs

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