SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs

Srikantaiah, Shekhar; Kandemir, Mahmut

doi:10.1007/978-3-642-11515-8_21

Cited by 4 publications

(9 citation statements)

References 21 publications

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“…Bitirgen et al [38] also proposed simultaneous cache and bandwidth allocation using machine learning; however, their technique provides no information about application slowdowns and requires a training phase. Srikantaiah et al [39] also propose simultaneous resource allocation, but they assume a simple exponentially decaying miss rate with increasing cache size, which is an oversimplification, as shown in Figure 6. Federova et al [40] examined OS-level scheduling to optimize CMT (multithread CMPs) performance; however, we are able to provide a finer grained control over application execution rates.…”

Section: Shared Resource Managementmentioning

confidence: 99%

TimeCube: A manycore embedded processor with interference-agnostic progress tracking

Gupta

Sampson

Taylor

2013

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

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Abstract-Recently introduced processors such as Tilera's Tile Gx100 and Intel's 48-core SCC have delivered on the promise of high performance per watt in manycore processors, making these architectures ostensibly as attractive for low-power embedded processors as for cloud services. However, these architectures space-multiplex the microarchitectural resources between many threads to increase utilization, which leads to potentially large and varying levels of interference. This decorrelates CPU-time from actual application progress and decreases the ability of traditional software to accurately track and finely control application progress, hindering the adoption of manycore processors in embedded computing.In this paper we propose Progress Time as the counterpart of CPU-time in space-multiplexed systems and show how it can be used to track application progress. We also introduce TimeCube, a manycore embedded processor that uses dynamic execution isolation and shadow performance modeling to provide an accurate online measurement of each application's Progress Time. Our evaluation shows that a 32-core TimeCube processor can track application progress with less than 1% error even in the presence of a 6× average worst-case slowdown. TimeCube also uses Progress Times to perform online architectural resource management that leads to a 36% improvement in throughput compared to existing microarchitectural resource allocation schemes. Overall, the results argue for adding the requisite microarchitectural structures to support Progress Time in manycore chips for embedded systems.

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Section: Shared Resource Managementmentioning

confidence: 99%

TimeCube: A manycore embedded processor with interference-agnostic progress tracking

Gupta

Sampson

Taylor

2013

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

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“…Specifically, each of the three controllers decides the resource allocations in their layer without considering the impact that the other may have on the performance. This can often lead to conflicting decisions in different resource allocations [17,18]. For example, at time t = 5, 5 cores, 16 cache ways and 80% of the off-chip memory bandwidth are allocated to the running application.…”

Section: Motivationmentioning

confidence: 99%

“…A multiple resource partitioning scheme called Symbiotic Resource Partitioning has been proposed in [18]. In this scheme, each of the shared cache space and off-chip memory bandwidth is partitioned dynamically based on the feedback from the partitioning of the other resource.…”

Section: Related Workmentioning

confidence: 99%

“…There are at least three fundamental shortcomings with such approaches: (i) Considering that system performance is heavily influenced by complex interactions among multiple resources [17,18], attempting to optimize performance/guarantee QoS by managing a single resource is not only less effective, but may also be impossible; (ii) In most existing schemes, there is no feedback among mechanisms, trying to provide QoS by managing different resources, and this leads to an anarchy in resource management; and (iii) Working with low-level resources like cache or memory-bandwidth restricts the system-performance metrics that can be controlled to only low-level metrics like IPC, which are not easily comprehended by system administrators or application programmers.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Mete

Sharifi

Srikantaiah

Mishra

et al. 2011

Proceedings of the ACM SIGMETRICS Joint International Conference on Measurement and Modeling of Computer Systems

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Management of shared resources in emerging multicores for achieving predictable performance has received considerable attention in recent times. In general, almost all these approaches attempt to guarantee a certain level of performance QoS (weighted IPC, harmonic speedup, etc) by managing a single shared resource or at most a couple of interacting resources. A fundamental shortcoming of these approaches is the lack of coordination between these shared resources to satisfy a system level QoS. This is undesirable because providing end-to-end QoS in future multicores is essential for supporting wide-spread adoption of these architectures in virtualized servers and cloud computing systems. An initial step towards such an end-to-end QoS support in multicores is to ensure that at least the major computational and memory resources on-chip are managed efficiently in a coordinated fashion.In this paper, we propose METE, a platform for end-to-end onchip resource management in multicore processors. Assuming that each application specifies a performance target/SLA, the main objective of METE is to dynamically provision sufficient on-chip resources to applications for achieving the specified targets. METE employs a feedback based system, designed as a Single-Input, Multiple-Output (SIMO) controller with an Auto-Regressive-Moving-Average (ARMA) model, to capture the behaviors of different applications. We evaluate a specific implementation of METE that manages cores, shared caches and off-chip bandwidth in an integrated manner on 8 and 16 core systems using a detailed full system simulator and workloads derived from the SPECOMP and SPECJBB multithreaded benchmarks. The collected results indicate that our proposed scheme is able to provision shared resources among co-runner applications dynamically over the course of execution, to provide end-to-end QoS and satisfy specified performance targets. Furthermore, the elegance of the control theory based multi-layer resource provisioning is in assuring QoS guarantees.

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“…Some studies proposed throttling or eliminating the useless/bad prefetches from consuming bandwidth [4,5,31,33], and tweaking the memory scheduling policy to prioritize demand and profitable prefetch requests [4,20]. Another method is to partition the off-chip bandwidth usage among cores [3,12,23,25,26,27,28,32], with partition sizes chosen to optimize a particular goal, such as to maximize throughput or fairness. However, these studies suffer from several drawbacks.…”

Section: Introductionmentioning

confidence: 99%

Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors

Liu

Solihin

2011

Proceedings of the ACM SIGMETRICS Joint International Conference on Measurement and Modeling of Computer Systems

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Modern high performance microprocessors widely employ hardware prefetching technique to hide long memory access latency. While very useful, hardware prefetching tends to aggravate the bandwidth wall, a problem where system performance is increasingly limited by the availability of the off-chip pin bandwidth in Chip Multi-Processors (CMPs).In this paper, we propose an analytical model-based study to investigate how hardware prefetching and memory bandwidth partitioning impact CMP system performance and how they interact. The model includes a composite prefetching metric that can help determine under which conditions prefetching can improve system performance, a bandwidth partitioning model that takes into account prefetching effects, and a derivation of the weighted speedupoptimum bandwidth partition sizes for different cores. Through model-driven case studies, we find several interesting observations that can be valuable for future CMP system design and optimization. We also explore simulation-based empirical evaluation to validate the observations and show that maximum system performance can be achieved by selective prefetching, guided by the composite prefetching metric, coupled with dynamic bandwidth partitioning.

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SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs

Cited by 4 publications

References 21 publications

TimeCube: A manycore embedded processor with interference-agnostic progress tracking

TimeCube: A manycore embedded processor with interference-agnostic progress tracking

Mete

Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors

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