Spur-reduction techniques for PLLs using sub-sampling phase detection

A 2.2GHz sub-sampling PLL with 0.16ps<inf>rms</inf> jitter and &#x2212;125dBc/Hz in-band phase noise at 700&#x00B5;W loop-components power

“…Compared with [1], the loop-components power is 8x lower while £ in-band is only 1dB worse. Compared with [2], the loop-components power is 3x lower while £ in-band is 4dB better. …”

“…3 shows the proposed Ref buffer, which exploits this property to drastically reduce power. A similar circuit has been used in [2] to control the Ref duty cycle. Here we exploit it to achieve low power.…”

“…Clock multiplication PLLs with very low jitter have recently been proposed based on sub-sampling [1,2] and injection locking [3,4]. In a PLL, the VCO dominates the out-of-band phase noise while the loop-components dominate the in-band phase noise.…”

“…In a PLL, the VCO dominates the out-of-band phase noise while the loop-components dominate the in-band phase noise. The sub-sampling (SS) PLL [1,2] can achieve very low in-band phase noise because: 1) divider noise is eliminated; 2) the phase detector (PD) and charge pump (CP) noise is not multiplied by N 2 . This paper describes a new SSPLL design aiming to drastically reduce the loop-components power while maintaining its superior in-band phase noise performance.…”

A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging

“…As only one edge is critical, big NMOS transistors are used for low noise while the PMOS is small and is controlled by its driver in such a way that simultaneous conduction of the PMOS and NMOS is reduced [26]. The driver (D1) of the PMOS is shown in Fig.…”