Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

Abstract

This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 m CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is 80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is 121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3 ps rms .

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

“…Secondly, we avoid any extra loading in the 60 GHz LO path as we utilize the dummy divider of the -path as will be explained in the PLL implementation section. Finally, this improves the isolation between the sampler and the oscillator, leading to reduced spurs as explained in [19].…”

A 3.45–4.22 GHz PLL frequency synthesizer with constant loop bandwidth for WLAN applications

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Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking

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