2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) 2017
DOI: 10.1109/edssc.2017.8126526
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Split-gate architecture for higher breakdown voltage in STI based LDMOS transistors

S. Ravi Teja
1
,
Mandar S. Bhoir
2
,
Nihar R. Mohapatra
3
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