/spl tau/AU: Timing analysis under uncertainty

Bhardwaj, Sarvesh; Vrudhula, Sarma; Blaauw, David

doi:10.1109/iccad.2003.159745

Cited by 35 publications

(25 citation statements)

References 8 publications

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“…Formulation (12) is a stochastic optimization problem. The statistical analysis and design of digital circuits is an area of growing interest and importance; see, e.g., Agarwal et al (2003), Bhardwaj et al (2003), Brambilla and Maffezzoni (2001), Jyu et al (1993), Orshansky et al (1999), and Orshansky and Keutzer (2002). This is still an active research area, and no consensus has emerged as to what the best statistical models are.…”

Section: Statistical Designmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

153

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Section: Statistical Designmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

153

146

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“…Suppose that each of the four physical parameters requires in its representation three principal components. From (22), path delay will be expanded in terms of 12 principal components. Fig.…”

Section: A Yield-margin Curves and Virtual Cornersmentioning

confidence: 99%

“…The aim is to extend traditional STA so that it takes into account statistical delay variations [5], [6], [16]- [22] leading to a statistical STA (SSTA). Given the difficulty of early estimation of systematic within-die variations, they have often been ignored; thus, within-die variations were accounted for on a random basis only [6], [13], [18], [21], [22], which is undesirable. In order to avoid making this assumption, one needs to express the within-die correlations with a model that can be easily built from process data.…”

Section: Introductionmentioning

confidence: 99%

A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis

Najm

Menezes

Ferzli

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-A model for process-induced parameter variations is proposed, combining die-to-die, within-die systematic, and withindie random variations. This model is put to use toward finding suitable timing margins and device file settings, to verify whether a circuit meets a desired timing yield. While this parameter model is cognizant of within-die correlations, it does not require specific variation models, layout information, or prior knowledge of intrachip covariance trends. The approach works with a "generic" critical path, leading to what is referred to as a "processspecific" statistical-timing-analysis technique that depends only on the process technology, transistor parameters, and circuit style. A key feature is that the variation model can be easily built from process data. The derived results are "full-chip," applicable with ease to circuits with millions of components. As such, this provides a way to do a statistical timing analysis without the need for detailed statistical analysis of every path in the design.Index Terms-Correlations, die-to-die variations, generic critical path, parametric yield, principal component analysis, statistical timing analysis, timing margin, virtual corner, within-die variations.

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“…It states that, given two random vectors V and W having the same variances (i.e., σ ii = γ ii ), if one of them is more correlated than the other (i.e., σ ij ≥ γ ij for all i = j) then (8) and (9) hold.…”

Section: N) Be Two Random Vectors Of Size N Both Multi-normallmentioning

confidence: 99%

“…In a number of cases [2,6,7,8], it has been assumed that within-die variations are totally uncorrelated, an assumption which is not true in practice. It is usually hard to express the correlations between within-die parameter variations with a model built from process data.…”

Section: Introductionmentioning

confidence: 99%

Statistical timing analysis with two-sided constraints

Heloue¹,

Najm²

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

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Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a "device file setting" that takes into account within-die statistical variations, and with which to run traditional static timing analysis in order to meet the desired yield. Using process-specific "generic paths" representing critical paths in a given process technology, our approach can be used early in the design process, most importantly during the pre-placement phase. Within-die variations are taken care of using a simple model that assumes positive correlation, which leads to upper and lower bounds on the timing yield. Our approach also handles both setup and hold timing constraints.

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/spl tau/AU: Timing analysis under uncertainty

Cited by 35 publications

References 8 publications

Digital Circuit Optimization via Geometric Programming

Digital Circuit Optimization via Geometric Programming

A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis

Statistical timing analysis with two-sided constraints

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