ABSTRACTWe present a test scheduling methodology for core-based system-on-chips that can avoid hot spots and allows tradeoff between physical power dissipation and overall test time. A mixed integer linear programming formulation is presented to globally perform the power-time tradeoff, satisfy constraints, and produce the SoC test schedule.
I. INTRODUCTIONUsing pre-designed cores to implement a system-on-chip can significantly shorten the design turnaround time and time-tomarket. However, this advantage brin…
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