Small Logarithmic Floating-Point Multiplier Based on FPGA and Its Application on MobileNet

Xiong, Botao; Fan, Sheng; He, Xintong; Xu, Tu; Chang, Yuchun

doi:10.1109/tcsii.2022.3205945

Cited by 9 publications

(6 citation statements)

References 13 publications

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“…The SFP<3, 3> multiplier consuming

10 \times

LUT6s has been discussed in Xilinx WP530 9 that is not available for larger mantissa field. For example, SFP<3, 4> and SFP<3, 5> multiplier require

25 \times

and

78 \times

LUT6s, respectively 10 . This drawback is solved in this brief that needs

13 \times

LUT6s for SLFP<3, 5> multiplier.…”

Section: Results Discussionmentioning

confidence: 99%

“…For example, SFP<3, 4> and SFP<3, 5> multiplier require 25Â and 78Â LUT6s, respectively. 10 This drawback is solved in this brief that needs 13Â LUT6s for SLFP<3, 5> multiplier. In addition, according to Xilinx WP530, 9 the larger exponent field also can reduce the quantization error.…”

Section: Comparison With Mac Circuits Based On Sfp Formatmentioning

confidence: 99%

“…However, there exist two drawbacks that should be solved. (1) The mantissa field of the SFP multiplier cannot be larger than 3‐bit, which cannot provide sufficient accuracy for MobileNet 10 . (2) The 16‐input adder tree is not efficient for mapping the most common

3 \times 3

kernel 11 .…”

Section: Introductionmentioning

confidence: 99%

“…(1) The mantissa field of the SFP multiplier cannot be larger than 3-bit, which cannot provide sufficient accuracy for MobileNet. 10 (2) The 16-input adder tree is not efficient for mapping the most common 3 Â 3 kernel. 11 Hence, the contributions of this brief are listed as follows.…”

mentioning

confidence: 99%

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LUT‐DSP usage trade‐off for re‐configurable convolution acceleration core based on small logarithmic floating point representation

Xiong,

Fan,

et al. 2023

Circuit Theory & Apps

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The challenge in designing the high‐performance field‐programmable gate array (FPGA)‐based convolution accelerator is to take full advantage of the on‐chip computing resources. The reported CNN accelerators always exhaust the on‐chip DSPs and leave other computing resources under‐utilized. Hence, this brief presents a novel convolution acceleration core based on the small logarithmic floating‐point (SLFP) format, which results in three contributions. (1) The SLFP<3,5> multiplier is only implemented with LUT6s and operates at 650 MHz with the aid of the carry chain, which provides sufficient accuracy for most CNNs. In addition, a similar structure can be used to implement a SLFP<3,5> divider. (2) The DSPs in the TWO24 SIMD mode are cascaded to implement a 9‐input adder tree. The sum of the multiples of elements (e.g., , ) is easily obtained by configuring the last DSP in the 9‐input adder tree in the accumulation mode, which can support more kernels (e.g., , ) with a high utilization rate (). (3) The convolution core based on the SLFP format only uses LUT6s and DSPs to achieve 1300 MOPS, 433 MOPS, and 81 MOPS for , , and kernel, respectively. In summary, the proposed convolution accelerator not only balances the resource usage of LUT6s and DSPs but also quantizes most CNN models using several simple scaling operations instead of a computing‐intensive retraining algorithm because the distribution of SLFP numbers is very similar to FP32 numbers.

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“…The SFP<3, 3> multiplier consuming

10 \times

LUT6s has been discussed in Xilinx WP530 9 that is not available for larger mantissa field. For example, SFP<3, 4> and SFP<3, 5> multiplier require

25 \times

and

78 \times

LUT6s, respectively 10 . This drawback is solved in this brief that needs

13 \times

LUT6s for SLFP<3, 5> multiplier.…”

Section: Results Discussionmentioning

confidence: 99%

Section: Comparison With Mac Circuits Based On Sfp Formatmentioning

confidence: 99%

3 \times 3

kernel 11 .…”

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

LUT‐DSP usage trade‐off for re‐configurable convolution acceleration core based on small logarithmic floating point representation

Xiong,

Fan,

et al. 2023

Circuit Theory & Apps

Self Cite

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show abstract

“…Floating point units are not only complex, but also require more area and hence more power consuming as compared to fixed point multipliers. And the complexity of the floating point unit increases as accuracy becomes a major issue [4]. Even a minute error in accuracy can cause major consequences.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of FPGA Based Complex Floating Point Multiplier using CIFM

et al. 2023

IJFMR

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: Floating point multiplication is one of the crucial operations in many application domains such as image processing, signal processing etc. But every application requires different working features. Some need high precision, some need low power consumption, low latency etc. The multiplication process requires more hardware resources and processing time when compared with addition and subtraction. This paper presents, Design and Implementation of FPGA based Complex Floating Point Multiplier using Combined Integer and Floating point Multiplier (CIFM). The Processing speed of the multipliers decides the execution time of the system as it consumes most of the time. The design is implemented in VHDL and design is synthesized on FPGA to know the performance. The architectures for the three multiplier solutions of complex multiplier for 32 x 32 bit complex numbers multiplication are coded in VHDL and implemented through Xilinx ISE 13.4 navigator and Modelsim 5.6 and their performance is compared. The complex floating point multiplication with single precision using CIFM multiplier has comparatively less amount of delay and power consumption with respect to Vedic and Array multiplier.

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A floating‐point multiplier based on angle representation method

Gan,

Wang,

Wang

et al. 2024

Circuit Theory & Apps

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SummaryThis article proposes a novel angle representation method for floating‐point number, which eliminates the need for DSP (Digital Signal Processor) resources and reduces the resource usage when performing floating‐point multiplication. Compared with the implementation of floating‐point multiplier using IP cores, the implementation of approximate multiplication based on lookup tables can achieve an average reduction of 58.2% in LUTs (look‐up tables) and an average increase of 20.4% in frequency for mantissa widths ranging from 3 to 12 bits. Additionally, it can also save an average of 23.2% in registers. Analysis of PDP (power‐delay product)/LUT to MRED (mean relative error distance)/PRED (probability of relative error distance) among other approximate multipliers shows that the proposed design extends the Pareto front. At last, simulation of a three‐level inverter is implemented to verify the effectiveness of the multiplier.

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Small Logarithmic Floating-Point Multiplier Based on FPGA and Its Application on MobileNet

Cited by 9 publications

References 13 publications

LUT‐DSP usage trade‐off for re‐configurable convolution acceleration core based on small logarithmic floating point representation

LUT‐DSP usage trade‐off for re‐configurable convolution acceleration core based on small logarithmic floating point representation

Design and Implementation of FPGA Based Complex Floating Point Multiplier using CIFM

A floating‐point multiplier based on angle representation method

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