Single-Event Sensitivity and Hardening of a Pipelined Analog-to-Digital Converter

Sternberg, Andrew L.; Massengill, L.W.; Hale, Mark D.; Blalock, B.J.

doi:10.1109/tns.2006.886204

Cited by 23 publications

(12 citation statements)

References 13 publications

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“…A SAR is chosen as an example due to the simplicity of examining subtraction across many stages. With an offset, the residue operation of (1) changes to (14) where in the SAR case, corresponds to a given stage fullscale range, which in a binary weighted SAR will decrease by a factor of two in each cycle.…”

Section: A Analysis Of Offsets In Residue Shapingmentioning

confidence: 99%

“…Redundancy is the act of performing extra quantization on the input to an ADC stage, while maintaining the same overall ADC resolution, in order to achieve a greater tolerance to nonideal effects that cause over-range errors. This allows for the ability to compensate for settling errors [3]- [5], reduce the impact of comparator offsets [6], [7], allow for PN injectable background calibration [8]- [12], permit advanced correlated double sampling techniques to reduce amplifier gain requirements [13], and enhance the radiation hardening of critical high stress ADCs [14], [15]. Generally, the resulting benefits of redundancy include increased speed, reduced circuit power and complexity, and the ability to compensate for device and environmental mismatches.…”

mentioning

confidence: 99%

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The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping

Guerber

Gande

Moon

2012

IEEE Trans. Circuits Syst. I

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Abstract-An analysis of the statistics of multistage (pipeline, SAR, and algorithmic) ADCs with redundancy is performed and the ability to achieve an extra 6 dB of resolution in ADCs with half-bit redundancy is shown due to probability density function (PDF) residue shaping. This paper classifies redundancy techniques to show that only some have properties leading to statistical resolution improvements. When properly implemented, resolution gains are maintained even in the presence of large sub-ADC nonlinearity. ADC design criteria for maximizing these resolution increases through PDF residue shaping are described including improved back-end ADCs, stage comparator offset bounds, and the use of scaled conventional restoring with Z added levels (CRZ) stage redundancy. PDF residue shaped structural improvements are also quantified in relation to ideal and nonideal traditional multistage ADC structures.

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Section: A Analysis Of Offsets In Residue Shapingmentioning

confidence: 99%

mentioning

confidence: 99%

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping

Guerber

Gande

Moon

2012

IEEE Trans. Circuits Syst. I

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“…Also, since a large number of comparators are used, ADC performance may be greatly degraded due to transistor variations caused by TID [6]. Pipelined ADCs can achieve high resolution, but performance can be degraded by TID because multiple amplifiers and comparators are used in its multi-stage structure [7]. Sigma-delta ADCs also offer very high resolution but are still affected by TIDs because of a large number of amplifiers and integrators [8].…”

Section: Radiation-hardened Adc Structurementioning

confidence: 99%

A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems

Min

Kang

et al. 2019

Sensors

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For stable and effective control of the sensor system, analog sensor signals such as temperature, pressure, and electromagnetic fields should be accurately measured and converted to digital bits. However, radiation environments, such as space, flight, nuclear power plants, and nuclear fusion reactors, as well as high-reliability applications, such as automotive semiconductor systems, suffer from radiation effects that degrade the performance of the sensor readout system including analog-to-digital converters (ADCs) and cause system malfunctions. This paper investigates an optimal ADC structure in radiation environments and proposes a successive- approximation-register (SAR) ADC using delay-based double feedback flip-flops to enhance the system tolerance against radiation effects, including total ionizing dose (TID) and single event effects (SEE). The proposed flip-flop was fabricated using 130 nm complementary metal–oxide–semiconductor (CMOS) silicon-on-insulator (SOI) process, and its radiation tolerance was measured in actual radiation test facilities. Also, the proposed radiation-hardened SAR ADC with delay-based dual feedback flip-flops was designed and verified by utilizing compact transistor models, which reflect radiation effects to CMOS parameters, and radiation simulator computer aided design (CAD) tools.

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“…It can be observed from Fig. 5, that the commonly used radiation hardening technique of increasing the capacitor value to decrease the transient effect will not only increase area and power consumption of the system but also reduce the maximum achievable sample rate of the system [2], [3], [14].…”

Section: A System Level Model For Seementioning

confidence: 99%

“…7. The voltage magnitude of the single event error source for each stage depends on the random charge transferred and the capacitance of the corresponding pipeline stage (1)(2)(3)(4)(5)(6). Equation (7) shows the error voltage source derived from a single event particle's energy source for the different stages of the pipeline ADC .…”

Section: B See Model For a Pipelined Adcmentioning

confidence: 99%

Detection and Correction Methods for Single Event Effects in Analog to Digital Converters

Venkatram

Guerber

Gande

et al. 2013

IEEE Trans. Circuits Syst. I

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This paper presents detection and correction methods for single event effects in analog to digital converters. Multi-path ADC based detection method is proposed for single event effects and bit error rate. Two correction schemes are proposed for single event effects based on multi-path ADC structure. 1) Two-path ADC based detection scheme with skip and fill algorithm based correction scheme. 2) Three-path ADC based detection scheme with majority voting based correction scheme. Advantages and limitations of both the methods are presented with simulation results. In particular, the three-path ADC can detect and correct for single event effects independent of repetition rate, magnitude of single event effects and the choice of data converter architecture. In three path ADC technique, the accuracy degradation is less than 1.7 dB or 0.28 bit for the Nyquist bandwidth for single event effects. Bit-Error Rate (BER) is effectively squared for three-path ADC as compared to a conventional ADC.Index Terms-Analog-digital conversion, bit error rate, metastability, pipeline ADC and multi-path ADC, radiation effects, radiation hardening by design, single event effects, single event upset, skip and fill interpolation, split-ADC technique, transient radiation effects.

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Single-Event Sensitivity and Hardening of a Pipelined Analog-to-Digital Converter

Cited by 23 publications

References 13 publications

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping

A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems

Detection and Correction Methods for Single Event Effects in Analog to Digital Converters

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