Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?

Chung, Eric S.; Milder, Peter; Hoe, James C.; Mai, Ken

doi:10.1109/micro.2010.36

Cited by 187 publications

(121 citation statements)

References 43 publications

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“…The estimated total power draw was 0.33 W, composed of 0.20 W of dynamic power and 0.13 W of idle power. The measured power reported for the Zedboard is 6.1 W [11], and the power consumption of a high-performance processor is approximately 90 W [12] (Intel Core i7). The power consumption of the proposed ROS-compliant FPGA component is therefore much lower than that of a PC.…”

Section: • Int16 Width: Image Width (16-bit Integer) • Int16 Height: mentioning

confidence: 99%

FPGA Components for Integrating FPGAs into Robot Systems

Ohkawa

Yamashina

Kimura

et al. 2018

IEICE Trans. Inf. & Syst.

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SUMMARYA component-oriented FPGA design platform is proposed for robot system integration. FPGAs are known to be a power-efficient hardware platform, but the development cost of FPGA-based systems is currently too high to integrate them into robot systems. To solve this problem, we propose an FPGA component that allows FPGA devices to be easily integrated into robot systems based on the Robot Operating System (ROS). ROS-compliant FPGA components offer a seamless interface between the FPGA hardware and software running on the CPU. Two experiments were conducted using the proposed components. For the first experiment, the results show that the execution time of an FPGA component for image processing was 1.7 times faster than that of the original software-based component and was 2.51 times more power efficient than an ordinary PC processor, despite substantial communication overhead. The second experiment showed that an FPGA component for sensor fusion was able to process multiple sensor inputs efficiently and with very low latency via parallel processing.

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Section: • Int16 Width: Image Width (16-bit Integer) • Int16 Height: mentioning

confidence: 99%

FPGA Components for Integrating FPGAs into Robot Systems

Ohkawa

Yamashina

Kimura

et al. 2018

IEICE Trans. Inf. & Syst.

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“…General purpose computing offers the flexibility to run arbitrary workloads but often exhibits less performance and energy efficiency than specialized hardware [1]. The term accelerator, a type of specialization, is often a bit ambiguous.…”

Section: Related Workmentioning

confidence: 99%

Quantifying acceleration: Power/performance trade-offs of application kernels in hardware

Reagen

Shao

Wei

et al. 2013

International Symposium on Low Power Electronics and Design (ISLPED)

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Abstract-As the traditional performance gains of technology scaling diminish, one of the most promising directions is building special purpose fixed function hardware blocks, commonly referred to as accelerators. Accelerators have become prevalent in industrial SoC designs for their low power, high performance potential. In this work we explore thousands of implementations of classical software workloads in hardware. This thorough, detailed design space search of hardware accelerators gives architects a quantitative way to reason about the differences in implementations. The exploration presented in this work shows that the space is full of poor design choices. By thoroughly analyzing each benchmark, we show which provide the most performance when implemented in hardware given a fixed power budget and explain which design techniques work best for each workload.

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“…Compared to homogeneous processors such as CPUs or GPUs, heterogeneous processors can deliver improved overall performance and power efficiency [29], while sufficient heterogeneous parallelisms exist. The main characteristics of heterogeneous processors include unified shared memory and fast communication among different types of cores (e.g., CPU cores and GPU cores).…”

Section: Introductionmentioning

confidence: 99%

Speculative segmented sum for sparse matrix-vector multiplication on heterogeneous processors

Liu

Vinter

2015

Parallel Computing

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Sparse matrix-vector multiplication (SpMV) is a central building block for scientific software and graph applications. Recently, heterogeneous processors composed of different types of cores attracted much attention because of their flexible core configuration and high energy efficiency. In this paper, we propose a compressed sparse row (CSR) format based SpMV algorithm utilizing both types of cores in a CPU-GPU heterogeneous processor. We first speculatively execute segmented sum operations on the GPU part of a heterogeneous processor and generate a possibly incorrect results. Then the CPU part of the same chip is triggered to re-arrange the predicted partial sums for a correct resulting vector. On three heterogeneous processors from Intel, AMD and nVidia, using 20 sparse matrices as a benchmark suite, the experimental results show that our method obtains significant performance improvement over the best existing CSR-based SpMV algorithms.

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Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?

Cited by 187 publications

References 43 publications

FPGA Components for Integrating FPGAs into Robot Systems

FPGA Components for Integrating FPGAs into Robot Systems

Quantifying acceleration: Power/performance trade-offs of application kernels in hardware

Speculative segmented sum for sparse matrix-vector multiplication on heterogeneous processors

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