Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

Park, Ki-Heung; Han, Kyoung-Rok; Kim, Young Min; Lee, Jong-Ho

doi:10.1109/led.2006.880833

Cited by 13 publications

(6 citation statements)

References 6 publications

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“…Note that the saddle FET 10,11) appears to have a similar structure to the proposed fin-RCAT, but the saddle FET has small portion of the vertical transistor and the electrical characteristics of the finFET (the bottom transistor) is improved by an elevated source/drain like structure and local channel doping. Its device design is different from that of the fin-RCAT.…”

Section: Device Designmentioning

confidence: 99%

Three Series-Connected Transistor Model for a Recess-Channel-Array Transistor and Improvement of Electrical Characteristics by a Bottom Fin Structure

Yoshida

Kahng

Moon

et al. 2009

jjap

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A three series-connected transistor model is introduced to understand the electrical characteristics of conventional recess-channel-array transistors (RCATs) and modified RCATs. An RCAT is considered to be a serial connection of three transistors consisting of one bottom transistor and two vertical transistors. The electrical characteristics of a cell transistor are explained by a balance of those transistors. A newly modified fin-RCAT which has a fin structure at the bottom of a silicon recess is proposed to improve cell transistor characteristics. This design improves cell current by 70% while maintaining retention characteristics.

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Section: Device Designmentioning

confidence: 99%

Three Series-Connected Transistor Model for a Recess-Channel-Array Transistor and Improvement of Electrical Characteristics by a Bottom Fin Structure

Yoshida

Kahng

Moon

et al. 2009

jjap

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“…Then, the RTN amplitude in the GIDL current estimated by the proposed model is compared against that obtained from the TCAD simulation data in Saddle Metal-Oxide-Semiconductor FieldEffect Transistor (Saddle MOSFET), as in [9,10].…”

Section: Introductionmentioning

confidence: 99%

Analysis and modeling for random telegraph noise of GIDL current in saddle MOSFET for DRAM application

Moon

Lee

Shin

et al. 2014

IEICE Electron. Express

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“…Especially, for a dynamic random access memory (DRAM) cell transistor, control of the OFF state leakage current to secure adequate retention time is an important issue. To reduce the leakage current, a novel concept of transistors such as the recess-channel-array Transistor (RCAT) 1) and the fin-type devices 2,3) has recently been reported. The idea of the RCAT is to increase the effective channel length by recessing the channel region.…”

Section: Introductionmentioning

confidence: 99%

Fin and Recess-Channel Metal Oxide Semiconductor Field Effect Transistor for Sub-50 nm Dynamic Random Access Memory Cell

Song

Kim

et al. 2010

Jpn. J. Appl. Phys.

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In this paper, we propose a novel fin and recess-channel metal oxide semiconductor field effect transistor (MOSFET) for sub-50 nm dynamic random access memory (DRAM) cell application. Also, it is compared with the recess-channel-array transistor (RCAT). In the proposed device, a silicon fin region is added to the recessed channel MOSFET. Thanks to the additional current path through the silicon fin with the wide source/drain width, the FiReFET shows excellent current drivability. To reduce gate-induced drain leakage (GIDL) current, we adopt an underlapped device structure. As a result, it is found that the optimized underlap structure helps to prevent the OFF state leakage current induced by the increase of the gate work function.

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Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

Cited by 13 publications

References 6 publications

Three Series-Connected Transistor Model for a Recess-Channel-Array Transistor and Improvement of Electrical Characteristics by a Bottom Fin Structure

Three Series-Connected Transistor Model for a Recess-Channel-Array Transistor and Improvement of Electrical Characteristics by a Bottom Fin Structure

Analysis and modeling for random telegraph noise of GIDL current in saddle MOSFET for DRAM application

Fin and Recess-Channel Metal Oxide Semiconductor Field Effect Transistor for Sub-50 nm Dynamic Random Access Memory Cell

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