Siamese-Twin: A Dynamically Fault-Tolerant Fat-Tree

Sem-Jacobsen, Frank Olaf; Skeie, Tor; Lysne, Olav; Toerudbakken, O.; Rongved, E.; Johnsen, Bjorn Dag

doi:10.1109/ipdps.2005.401

Cited by 16 publications

(17 citation statements)

References 28 publications

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“…The work proposed in [14] uses two parallel fattrees with crossover links between the switches at the same position of each network to provide dynamic faulttolerance, but at a high hardware cost. In [15], the authors use several parallel MINs to create redundancy without any interconnecting link between them, also increasing the hardware cost of the network.…”

Section: Related Workmentioning

confidence: 99%

A Family of Fault-Tolerant Efficient Indirect Topologies

Garzon

Requena

Gómez

et al. 2016

IEEE Trans. Parallel Distrib. Syst.

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Abstract-On the one hand, performance and fault-tolerance of interconnection networks are key design issues for high performance computing (HPC) systems. On the other hand, cost should be also considered. Indirect topologies are often chosen in the design of HPC systems. Among them, the most commonly used topology is the fat-tree. In this work, we focus on getting the maximum benefits from the network resources by designing a simple indirect topology with very good performance and fault-tolerance properties, while keeping the hardware cost as low as possible. To do that, we propose some extensions to the fat-tree topology to take full advantage of the hardware resources consumed by the topology. In particular, we propose three new topologies with different properties in terms of cost, performance and fault-tolerance. All of them are able to achieve a similar or better performance results than the fat-tree, providing also a good level of fault-tolerance and, contrary to most of the available topologies, these proposals are able to tolerate also faults in the links that connect to end nodes.

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Section: Related Workmentioning

confidence: 99%

A Family of Fault-Tolerant Efficient Indirect Topologies

Garzon

Requena

Gómez

et al. 2016

IEEE Trans. Parallel Distrib. Syst.

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“…Although the probability of failure of an individual component is low, the probability of any of the multitude of components making up the interconnection network failing quickly becomes nonnegligible as the network size increases [6]. Furthermore, CMOS devices are becoming increasingly susceptible to external effects such as electrical noise, process variation, and natural radiation [7].…”

Section: Introductionmentioning

confidence: 99%

“…With migration toward high-radix routers, the lower-radix topologies and their routing scheme such as the cyclic Banyan networks are no longer suitable. The simple adaptive routing schemes for the dynamic fault tolerance of fat-trees were proposed [6,18].…”

Section: Introductionmentioning

confidence: 99%

The deflection self-routing Delta network: a dynamically fault-tolerant high-radix multistage interconnection network

Park

2009

J Supercomput

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High-radix multistage interconnection networks are popular interconnection technologies for parallel supercomputers and cluster computers. In this paper, we presented a new dynamically fault-tolerant high-radix multistage interconnection network using a fully-adaptive self-routing. To devise the fully-adaptive self-routing for recovering the misrouting around link faults in such network, we introduce an abstract algebraic analysis of the topological structure of the high-radix Delta network. The presented interconnection network provides multiple paths by using all the links of all the stages of the network. We also present a mathematical analysis of the reliability of the interconnection network for quantitative comparison against other networks. The MTTF of 64 × 64 network proposed is 2.2 times greater than that of the cyclic Banyan network. The hardware cost of the proposed network is half that of the cyclic Banyan network and the 2D ring-Banyan network.

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“…In this technique, if a given destination is not reachable due to faults in one of the networks, packets to that destination are sent through any of the other parallel MINs. In [116], a new topology that consists of two parallel fattrees with crossover links between the switches in the same position in both networks is proposed. In this topology, when a packet encounters a fault in its path, it is forwarded through the crossover link to the other parallel fat-tree.…”

Section: Fault-tolerance In Minsmentioning

confidence: 99%

“…For instance, larger buffers can be introduced, doubling switch storage capability, thus keeping the same buffer resources of the fat-tree. Another possibilities are to replicate the network to deal with higher traffic loads like in [21], or to provide fault-tolerance like in [116].…”

Section: Advantages and Disadvantagesmentioning

confidence: 99%

Low-Memory Techniques for Routing and Fault-Tolerance on the Fat-Tree Topology

Requena¹

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Siamese-Twin: A Dynamically Fault-Tolerant Fat-Tree

Cited by 16 publications

References 28 publications

A Family of Fault-Tolerant Efficient Indirect Topologies

A Family of Fault-Tolerant Efficient Indirect Topologies

The deflection self-routing Delta network: a dynamically fault-tolerant high-radix multistage interconnection network

Low-Memory Techniques for Routing and Fault-Tolerance on the Fat-Tree Topology

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