SEU mitigation testing of Xilinx Virtex II FPGAs

Yui, C.; Swift, G.M.; Carmichael, C.; Koga, R.; George, J.

doi:10.1109/redw.2003.1281354

Cited by 52 publications

(22 citation statements)

References 2 publications

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“…The novel approach, here proposed for fast detecting and correcting SEU-induced configuration errors, exploits the internal dynamic partial readback and reconfiguration capabilities introduced in the XILINX Virtex FPGA families, extensively employed in numerous space missions [12][13]. Error Detection And Correction (EDAC) Hamming Codes [14] of the configuration bitstream are precomputed by an on purpose software, and then stored in a TMR-ed reference memory inside the SFPGA during its first configuration.…”

Section: Fig 1 Traditional Rhdb Methodologies; (A) the Tmr Solutionmentioning

confidence: 99%

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

Lanuzza

Zicari

Frustaci

et al. 2009

Lecture Notes in Computer Science

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Abstract. This paper presents an efficient approach to protect an FPGA design against Single Event Upsets (SEUs). A novel configuration scrubbing core, instantiated at the top level of the user project, is used for internal detection and correction of SEU-induced configuration errors without requiring further external radiation hardened control hardware. As demonstrated in the paper, this approach combines the benefits of fast SEU faults detection with fast restoration of the device functionality and small overhead. Moreover, the proposed technique result highly versatile and can be adopted for different FPGA device families.

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Section: Fig 1 Traditional Rhdb Methodologies; (A) the Tmr Solutionmentioning

confidence: 99%

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

Lanuzza

Zicari

Frustaci

et al. 2009

Lecture Notes in Computer Science

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“…An external scrubber in combination with TMR was successfully tested on a Virtex-II X-2V1000 device in [37]. The scrubber (referred as configuration monitor) was implemented on an auxiliary FPGA under the control of a host computer.…”

Section: A External Vs Internal Scrubbermentioning

confidence: 99%

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

Herrera-Alzu

López‐Vallejo

2013

IEEE Trans. Nucl. Sci.

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Abstract-SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers.

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“…Using basic SEU mitigation by dedicated design measures (e.g. in operation functional testing of the device, configuration memory scrubbing, Triple Modular Redundancy, TMR) the expected SEU rates for a broad range of applications can be reduced to negligible or at least tolerable values [5], [6]. Zero effective upsets is not our objective, but to achieve the optimum availability for given system constraints (cost, performance, mass, etc.…”

Section: Soc Dpu Design Variantsmentioning

confidence: 99%

Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments

Fiethe

Michalik

Dierker

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Individual Data Processing Units (DPUs) are commonly used for operational control and specific data processing of scientific space instruments. To overcome the limitations of traditional rad-hard or fully commercial design approaches, a System-on-Chip (SoC) solution based on state-of-the-art FPGA is introduced. This design has been successfully demonstrated in space on Venus Express. From this, a reconfigurable DPU design for future advanced imaging sensors is derived using embedded processing cores. In addition, a SoC design variant is presented based on recently available FPGA technology with integrated hardwired processor, which is capable to support also high end payload applications.

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SEU mitigation testing of Xilinx Virtex II FPGAs

Cited by 52 publications

References 2 publications

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments

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