Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility

Ottavi, Marco; Asciolla, Dario; Fiorucci, Tiziano; Grosso, Erica Del; Marzullo, Carla; Scaramella, Alessandro; Stramaccioni, Simone; Zibecchi, Alessia; Cardarilli, G.C.; Cazzaniga, Carlo; Nunzio, Luca Di; Fazzolari, Rocco; Re, M.; Reviriego, Pedro; Furano, Gianluca; Senesi, R.

doi:10.1109/dtis.2018.8368564

Cited by 2 publications

(2 citation statements)

References 3 publications

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“…The extensive usage of commercial fault injection tools like the ones provided by Cadence [15] or Synopsys [16] guarantees the proper exploration of the behaviour of the DUT when subject to SEU or other types of faults. This allows the Verification Engineers to have an idea of the behavior of their design without the need to move onto practical testing in radiation environments, which require a dedicate setup [17] and an expensive and not widely available infrastructure.…”

Section: Methodsmentioning

confidence: 99%

Software Product Reliability Based on Basic Block Metrics Recomposition

Fiorucci

Natale

Daveau

et al. 2022

2022 IEEE 28th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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In the context of functional verification, the focus has always been on hardware and its ability to be both resilient to errors and to recover from them autonomously. In order to evaluate these characteristics, an extensive use of Fault Injection tools is made to achieve clear and granular results. These testing campaigns are carried out on the entire DUT and require a consistent amount of time and computational resources. The possibility of reducing these costs applying modern techniques as the study of the Dysfunctional State Machine or the proof of concept regarding the composability of single block fault injection campaigns to obtain a library of component of which the reliability metrics are well known, as already been extensively discussed and proven on hardware. In this work instead the application of this methodologies to software is presented for the first time. In order to do so, the software has been divided into basic block, atomic chunks of code having precise carachteristics that will ensure the possibility to study them singularly and then recompose them into a software product which reliability metrics are known, without the need for complete Fault injection campaign.

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Section: Methodsmentioning

confidence: 99%

Software Product Reliability Based on Basic Block Metrics Recomposition

Fiorucci

Natale

Daveau

et al. 2022

2022 IEEE 28th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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“…The cross-section uses the number of errors and the fluence η. Fluence is the fraction of the flux (neutrons/cm 2 ṡ) that impacted the DUT during the experiment. As the beamline has a homogeneous distribution of particles [13], we just need to multiply the benchmark's execution time for each of the runs. The cross-section is proportional to the number of errors, highlighting the importance of not overestimating the error count.…”

Section: Characterising Soft Processor Coresmentioning

confidence: 99%

An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?

Forlin,

van Huffelen,

Cazzaniga

et al. 2023

2023 IEEE European Test Symposium (ETS)

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Fast development, low cost, and reconfigurability are becoming critical factors for aerospace applications, making SRAM FPGAs attractive. However, SRAM FPGAs are prone to errors in the user and on the configuration bits. For their correct functioning, they must be capable of withstanding failures without sacrificing much performance. When adjusting a soft core for these applications, it is essential to know where redundancies are necessary, to avoid unnecessary overhead. We characterize the reliability of an unprotected RISC-V microcontroller using an accelerated neutron beam. Our investigation shows that, for our chosen benchmark and processor, the user data in the memory banks is the leading cause of the total number of errors in the application. By reversing the benchmark operations, we could root cause the origin of the observed errors and found that most of the data corruption detected during the runs stem from previously corrupt input data or from output data that were corrupted while transmitting.

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Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility

Cited by 2 publications

References 3 publications

Software Product Reliability Based on Basic Block Metrics Recomposition

Software Product Reliability Based on Basic Block Metrics Recomposition

An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?

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