Self-tuning Intel Restricted Transactional Memory

Migration in Hardware Transactional Memory on Asymmetric Multiprocessor

“…If the transaction fails due to capacity overflow, the maximum number of repetitions is cut in half. The algorithm used is one of the algorithms described in [48], which provides satisfactory results for almost all applications. Before starting the transaction, each thread will wait for some pseudorandom time, which is generated from a range that grows exponentially with the number of repetitions of that particular transaction.…”

An Analytical Model of Hardware Transactional Memory

“…Black box techniques for throughput prediction are present in the literature for the case of STM [5], [31], and also in HTM either to predict its throughput [29] or to improve its performance by tuning the TM parameters [11], [15], [10]. Unlike the white-box analytical model presented in this model, which can be instantiated by simply providing a few parameters as input, these black box models require an extensive training phase.…”

“…While a number of alternative HTM designs have been proposed in the literature, the HTM implementations that are currently commercially available [24], [30] are built as relatively non-intrusive extensions of the cache coherency algorithm and, as such, suffer from several restrictions [16], [20]. Overall, make the performance of HTM is much dependent on a number of workload parameters and architectural design choices [16], [20], [28], [15], [10] -which makes the problem of predicting the performance achievable by HTM-based applications a very challenging task.…”