DOI: 10.1109/isscc.1981.1156232
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T. Nakamura, T. Miyazaki, S. Takahashi, T. Kure, T. Okabe, M. Nagata

Abstract: VARIOUS SELF-ALIGNED fabrication technologies have been proposedl " to realize high packing density and high speed bipolar LSIs and 12L LSIs. The self-aligned processes reported in these papers are used to reduce parasitic capacitances and cell areas.Junction capacitances between base and collector regions ( CBC) have drastic influences on high speed operation of bipolar devices. In addition, in 12L devices, the reduction of extrinsic base areas leads to the decrease of minority carriers injected into the …

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