2001
DOI: 10.1116/1.1406154
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Self-aligned process for single electron transistors

Abstract: Articles you may be interested inFabrication of nanogapped single-electron transistors for transport studies of individual single-molecule magnets

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Cited by 4 publications
(4 citation statements)
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“…The slight off-set of the simulated data points is within expectation as explained elsewhere. 34 Upon annealing in an oxygen atmosphere at a temperature of 900 1C, i.e. 32 The stoichiometry of the layers was probed by RBS and ERD (see Table 1).…”
Section: Resultsmentioning
confidence: 99%
“…The slight off-set of the simulated data points is within expectation as explained elsewhere. 34 Upon annealing in an oxygen atmosphere at a temperature of 900 1C, i.e. 32 The stoichiometry of the layers was probed by RBS and ERD (see Table 1).…”
Section: Resultsmentioning
confidence: 99%
“…As the difference between Au 5 Al 2 ͑−20.0 kJ/ mol͒ and Au 2 Al ͑−19.8 kJ/ mol͒ is negligibly small thermodynamically, either could be the preferable and primary intermetallic. In thin film studies ͑where Al and Au films were deposited one by one without breaking the vacuum͒ x-ray diffraction and Rutherford backscattering spectrometry found Au 5 Al 2 was the formed initially, [28][29][30]46 while elsewhere Au 5 Al 2 and Au 2 Al reportedly grew simultaneously. 47 During annealing, Majni et al 30 found that Au 2 Al was the second phase to appear while Xu et al 28,29 showed that Au 4 Al was formed after Au 5 Al 2 .…”
Section: -5mentioning
confidence: 99%
“…4,5 With the annealing step, pitting is observed easily on the source/drain regions of the NMOS transistors etched using recipe B. The annealing step performed in the second experiment will activate the gate dopants, thus enhancing the etch rate variation between the dual-doped gates.…”
Section: Physical Characterizationmentioning
confidence: 99%
“…4,5 For older generation ͑Ͼ0.25 m͒ technologies, Si pitting has not been reported to cause any significant shift in device characteristics. For example, ͑a͒ the lower portion of the wafer farthest from the gas pump is found to etch faster than the portion nearer to the pump, ͑b͒ the outermost regions of nested lines etch faster than the inner regions, 1-3 and ͑c͒ n-type doped polysilicon gates etch faster than p-type doped gates for dualdoped gate technology.…”
Section: Introductionmentioning
confidence: 99%