Self-aligned double patterning aware pin access and standard cell layout co-optimization

Abstract

Self-Aligned Double Patterning (SADP) is being considered for use at the 10nm technology node and below for routing layers with pitches down to ∼50nm because it has better LER and overlay control compared to other multiple patterning candidates. To date, most of the SADP-related literature has focused on enabling SADP-legal routing in physical design tools while few attempts have been made to address the impact SADP routing has on local, standard cell (SC) I/O pin access. In this paper, we present the first study on SADP-aware pin access and layout optimization at the SC level. Accounting for SADP-specific design rules, we propose a coherent framework that uses Mixed Integer Linear Programming (MILP) and branch and bound method to simultaneously optimize SADP-based local pin access and within-cell connections. Our experimental results show that, compared with the conventional approach, our framework effectively improves pin access of the standard cells and maximizes the pin access flexibility for routing.

Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line

“…Our cell routing framework is targeting at 10nm technology node with SADP process. The regular gridded based design rules [19] and SADP-specific design rules [20] are adapted in our work.…”

“…CA strips can be extended in vertical direction to make power and ground connections to the transistors or to connect P transistors and N transistors together. All the Metal-1 and MOL wires must be compliant with a set of design rules [19,20]. Since CA and Metal-1 are different layers, intersection of two perpendicular wire segments is allowed.…”

“…Utilizing grid graph effectively can simplify design rules. Since the SADP-specific parameters in [20] are much smaller than the grid width, the layout derived from the grid graph is SADP friendly intrinsically.…”

“…The rules to check whether there is any conflict between route r p i and route r q j are adapted from the 1-D gridded design rules in [19] and the SADP-specific design rules in [20].…”

“…There are some cell synthesis works for conventional 2D cells [14,15], or 1D cells [16,17,18,19]. Recently, an I/O pin extension approach was proposed to alleviate the pin access problem [20]. However, these existing studies suffer from one or more of the following issues.…”