Self-Aligned Contact Doping of WSe₂ Metal–Insulator–Semiconductor Field-Effect Transistors Using Hydrogen Silsesquioxane

Abstract

Conventional semiconductor fabrication methods are unsuitable for manufacturing two-dimensional material-based devices owing to the possibility of material contamination or damage, which significantly affects the device properties. In this study, the self-aligned contact doping method and remote oxygen plasma treatment were used to fabricate a WSe 2 -based topgate field-effect transistor (FET) with minimal contamination and damage. The results of Raman spectroscopy and capacitance−voltage measurement indicated that neither the WSe 2 nor the gate dielectric was damaged by the remote oxygen plasma. Additionally, the current−voltage measurement results exhibited excellent on/off ratio and field-effect mobility. The developed method can be used to fabricate FETs which have significantly high carrier concentrations and derive excellent electrical characteristics from WSe 2 -based devices. Therefore, the proposed process can serve as an effective device manufacturing method in the future.

Self-Aligned Top-Gate Structure in High-Performance 2D p-FETs via van der Waals Integration and Contact Spacer Doping

“…Our method involves self-aligned TG stacks by van der Waals (vdW) integration, followed by oxygen plasma doping at contact and spacer regions of FETs. Unlike conventional methods, , we demonstrate exceptional electrostatic controllability of 2D p-FETs realized by transferring TG stacks consisting of metal and hBN. The utilization of the self-aligned TG as doping-mask, coupled with subsequent large scale processing compatible oxygen plasma doping, results in a high on/off current ratio of 2.5 × 10 7 , small subthreshold swing ( SS ) of 98 mV dec –1 , and near-zero threshold voltage ( V th ) in WSe 2 p-FETs.…”

“…Next, we performed TG operations on the WSe 2 p-FETs. Figure a represents band structures of the WSe 2 p-FETs fabricated using conventional approach with partially metal covered hBN TG stack following the previous reports. , In this fabrication process, we transferred a 2 μm long hBN and subsequently patterned a 500 nm long TG electrode. The partially metal covered hBN TG stack results in unsatisfactory electrostatic controllability of 2D p-FET, as depicted in Figure b,c.…”

“…Solid-state surface charge transfer doping (SCTD) using nonstoichiometric oxide has been proposed as a facile hole doping method for achieving high hole doping concentrations in 2D materials. ,− For example, there have been recent reports on a reliable p-type SCTD technique using the oxidized 2D materials, e.g., WSe x O y formed upon oxidation of WSe 2 , from which high hole concentration was induced. , Nonetheless, SCTD applied to 2D materials tends to result in the absence of an off-current state with constantly high on-current, making them unsuitable for use in switching devices. To address this limitation, the lateral junction devices are proposed by patterning the doping profile of the channel area, offering improved electrostatic controllability of oxidized WSe 2 FETs through the generation of a built-in potential. ,,,− Furthermore, using a top-gate (TG) to modulate the built-in potential can be an effective approach for achieving high-performance p-FETs. , However, achieving a narrow top-gate length ( L tg ) in the R&D environment is challenging when using conventional top-gate fabrication methods that employ oxygen plasma doping at the spacer area. Additionally, challenges are presented when 2D materials are employed as a channel, e.g., transfer of dielectric layer and additional lithographic patterning process to precisely positioning TG electrodes, which limit the yield of fabrication process contributing to realization of high-performance p-FETs and p-type metal-oxide-semiconductor (PMOS) inverter …”

“…3,13,14,21−23 Furthermore, using a top-gate (TG) to modulate the built-in potential can be an effective approach for achieving highperformance p-FETs. 22,23 However, achieving a narrow topgate length (L tg ) in the R&D environment is challenging when using conventional top-gate fabrication methods that employ oxygen plasma doping at the spacer area. Additionally, challenges are presented when 2D materials are employed as a channel, e.g., transfer of dielectric layer and additional lithographic patterning process to precisely positioning TG electrodes, which limit the yield of fabrication process contributing to realization of high-performance p-FETs and p-type metal-oxide-semiconductor (PMOS) inverter.…”

Synthesis of a Tellurium Semiconductor with an Organic–Inorganic Hybrid Passivation Layer for High-Performance p-Type Thin Film Transistors

“…With the rapid increase in demand for new kinds of materials for future nanoelectronics, two-dimensional (2D) nanomaterials, such as graphene and transition-metal dichalcogenides (TMDs), have been regarded as promising materials owing to their extraordinary properties and atomic thicknesses. – TMD materials such as molybdenum disulfide and tungsten disulfide have been widely studied as an n-type channel layer of high-performance thin-film transistor (TFT), where the high-quality TMD film can be mostly obtained via chemical vapor deposition, which requires a high growth temperature over 900 °C; , thus, it suffers from integration with devices that undergo the fabrication at relatively low temperatures. In addition to TMD materials, oxide semiconductor-based TFTs also have been developed as n-type TFTs, where recent works have shown the amorphous indium–gallium-zinc-oxide TFTs via low-temperature fabrication and other oxide semiconductor-based TFTs with solution-driven gate dielectrics. – Considering that p-channel TFT is highly needed to implement complementary metal-oxide semiconductor logic circuits, a new class of p-type channels is required to develop high-performance devices with a low processing temperature.…”