DOI: 10.1109/date.2003.1253781
View full text
|
|
Share

Abstract: AbstractThis paper proposes Selectively Clocked Logic (SCL) style based on skewed logic for noise-tolerant low-power high-performance applications. Variations of the logic style with multiple threshold voltage (MV th -SCL) and multiple oxide thickness (Mt ox -SCL) techniques are also studied. Simulation results indicate that SCL, MV th -SCL, and Mt ox -SCL circuits reduce the total power consumption (leakage plus switching power) of the ISCAS benchmark circuits by 51.5%, 53.1%, and 69.6%, respectively, with o…

expand abstract