SD-VBS: The San Diego Vision Benchmark Suite

Venkata, Sravanthi Kota; Ahn, Ikkjin; Jeon, Dong‐Hwan; Gupta, Amit Kumar; Louie, Christopher; Garcia, Saturnino; Belongie, Serge; Taylor, Michael

doi:10.1109/iiswc.2009.5306794

Cited by 163 publications

(60 citation statements)

References 20 publications

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“…However, as we will show, static core fusion may not be the perfect match for all situations. Figure 2 plots the Instruction Per Cycle (IPC) performance variation over the execution of the Disparity Benchmark [25] on a fused 4-cores and 16-cores processor. On 4 cores, the performance oscillates between an IPC of 2 and 6 depending on the phase while on 16 cores the IPC can be as high as 16.…”

Section: Dynamic Core Fusionmentioning

confidence: 99%

“…For this paper we study the performance of a Dynamic Multicore Processor (DMP) on a set of vision benchmarks designed for hardware and compiler research [25]. The San Diego Vision Benchmark suite (SD-VBS) is composed of nine single-threaded C benchmarks ranging from image analysis to motion tracking.…”

Section: Benchmarksmentioning

confidence: 99%

“…We then discuss how classical loop optimizations such as unrolling can have a large impact on performance when fusing cores. Using the San Diego Vision Benchmark Suite [25] (SD-VBS) as a use case, we show that programs exhibit various phases with di erent amounts of ILP. We then perform a limit study on the potential for decreasing energy consumption while maintaining performance when adapting the number of cores for each program phase.…”

Section: Introductionmentioning

confidence: 99%

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A Study of Dynamic Phase Adaptation Using a Dynamic Multicore Processor

Micolet

Smith

Dubach

2017

ACM Trans. Embed. Comput. Syst.

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Heterogeneous processors such as ARM's big.LITTLE have become popular for embedded systems. They o er a choice between running workloads on a high performance core or a low-energy core leading to increased energy e ciency. However, the core con gurations are xed at design time which o ers a limited amount of adaptation. Dynamic Multicore Processors (DMPs) bridge the gap between homogeneous and fully recon gurable systems. Cores can fuse dynamically to adapt the computational resources to the needs of di erent workloads. There exists multiple examples of DMPs in the literature, yet the focus has mainly been on static partitioning. This paper conducts the rst thorough study of the potential for dynamic recon guration of DMPs at runtime. We study how performance varies with static partitioning and what software optimizations are required to achieve high performance. We show that energy consumption is reduced considerably when adapting the number of cores to program phases, and introduce a simple online model which predicts the optimal number of cores to use to minimize energy consumption while maintaining high performance. Using the San Diego Vision Benchmark Suite as a use case, the dynamic scheme leads to ∼ 40% energy savings on average without decreasing performance.

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Section: Dynamic Core Fusionmentioning

confidence: 99%

Section: Benchmarksmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Study of Dynamic Phase Adaptation Using a Dynamic Multicore Processor

Micolet

Smith

Dubach

2017

ACM Trans. Embed. Comput. Syst.

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“…Real-life applications have been used to run the experiments, selected from well-known benchmarking suites, namely PARSEC [3] (blackscholes, bodytrack, swaption, x264), SPEC [19] (h264), and Vision [9] (disparity, texture). These applications have been selected to represent a good mix of heterogeneous behaviors.…”

Section: A Experimental Setupmentioning

confidence: 99%

Combined on-line lifetime-energy optimization for asymmetric multicores

Bolchini

Carminati

Mitra

et al. 2016

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Abstract-In this paper we present an architectural and online resource management solution to optimize lifetime reliability of asymmetric multicores while minimizing the system energy consumption, targeting both single nodes (multicores) as well as multiple ones (cluster of multicores). The solution exploits the different characteristics of the computing resources to achieve the desired performance while optimizing the lifetime/energy tradeoff. The experimental results show that a combined optimization of energy and lifetime allows for achieving an extended lifetime (similar to the one pursued by lifetime-only optimization solutions) with a marginal energy consumption detriment (less than 2%) with respect to energy-aware but aging-unaware systems.

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“…We ported KMeans, a data clustering benchmark and Labyrinth, a maze-routing benchmark, from STAMP [20]. Power is a power pricing benchmark from JOlden [21] and Tracking is a vision benchmark from the SDVBS [22] …”

Section: Benchmarksmentioning

confidence: 99%

Using Disjoint Reachability for Parallelization

Jenista

Eom

Demsky

2011

Lecture Notes in Computer Science

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Abstract. We present a disjoint reachability analysis for Java. Our analysis computes extended points-to graphs annotated with reachability states. Each heap node is annotated with a set of reachability states that abstract the reachability of objects represented by the node. The analysis also includes a global pruning step which analyzes a reachability graph to prune imprecise reachability states that cannot be removed with local reasoning alone. We have implemented the analysis and used it to parallelize 9 benchmarks. Our evaluation shows the analysis results are sufficiently precise to parallelize our benchmarks and achieve an average speedup of 16.9×.

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SD-VBS: The San Diego Vision Benchmark Suite

Cited by 163 publications

References 20 publications

A Study of Dynamic Phase Adaptation Using a Dynamic Multicore Processor

A Study of Dynamic Phase Adaptation Using a Dynamic Multicore Processor

Combined on-line lifetime-energy optimization for asymmetric multicores

Using Disjoint Reachability for Parallelization

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