Scheduling of DSP Algorithms onto Heterogeneous-Multiprocessors with Inter-Processor Communication

Itradat, Awni; Ahmad, Munir; Shatnawi, Anas

doi:10.1109/newcas.2005.1496751

Cited by 5 publications

(3 citation statements)

References 5 publications

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“…These latest and earliest firing times are found relative to a reference node and are the result of intra and inter iteration precedence constraints. The detailed scheduling algorithm can be found in [11].…”

Section: B Time and Processor Schedulesmentioning

confidence: 99%

Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs

Itradat

Ahmad

Shatnawi

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a new technique for the minimization of I/O delay in the architectural synthesis of cyclic data flow graphs (DFG) representing DSP algorithms taking into consideration the inter-processor communication delays. In this paper, the question of optimizing the I/O delay without scarifying the iteration period (throughput) with non-negligible inter-processor communication overhead is addressed. The proposed technique operating on the cyclic DFG of a DSP algorithm is designed to evaluate the relative firing times of the nodes by using Floyd-Warshall's longest path algorithm so that the inter-processor communication overhead is taken into consideration to provide an optimized time and processor schedule. Moreover, the proposed scheme is applied to wellknow DSP benchmarks and seen that it is efficient in minimizing the I/O delay without scarifying the iteration period. I.INTRODUCTION Some of the applications that need a high-level synthesis are digital signal processing (DSP), communications, and image processing. These applications are among the most important applications that demand high computational power, and must be executed at a very high speed to enable real-time processing. Due to the parallelism within the DSP applications, parallel processing architectures are a natural choice for the synthesis of these applications. The problem of architectural synthesis for iterative algorithms has received a great deal of attention in recent years. However, most of the techniques for multiprocessor scheduling deal with a simplified problem in which the time to communicate data from one processor to another (interconnect delay) is not taken into consideration [1], thus eventually leading to unrealistic schedules. Well-known examples of such techniques are a cyclo-static scheduling method that uses exhaustive search [2] and the optimum unfolding technique [3]. These methods have one thing in common in that they have not considered the inter-processor communication delays (ICD). Curtis and Madisetti [4] have shown that inclusion of the ICDs is essential in a realistic development of multiprocessor schedules. Their objective was to use realistic structural and behavioral level description of a DSP algorithm that takes into consideration the ICDs to find simultaneously rate optimal and processor optimal schedules. They developed the so called DSMP-C1 method for this purpose. However, this method is computationally intensive, practical only for small DSP algorithms, and suitable for homogeneous multiprocessor systems. The techniques proposed in [5 ,6 ] use integer linear programming (ILP) to consider the inter-processor communication delay during the scheduling of the DSP applications mapped onto pre-defined homogeneous multiprocessor systems with different topologies

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Section: B Time and Processor Schedulesmentioning

confidence: 99%

Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs

Itradat

Ahmad

Shatnawi

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…The chosen node is scheduled to fire at a control step that would results in a minimum number of functional units required. Taking into account that the target multiprocessor system can contains both heterogeneous and/or general purpose functional units, a modification for the original scheduling technique in [4,5] is introduced. We defined the level of a control step to be the summation of sub-levels of the different types of operations and given by ... .…”

Section: Time Schedulementioning

confidence: 99%

“…The result of the time schedule is a set of firing times of all nodes. A Detailed version of the time schedule can be found in [5].…”

Section: Time Schedulementioning

confidence: 99%

A Processor Allocation of DSP Applications Onto Heterogeneous Multiprocessor Architectures

Itradat¹,

Ahmad²,

Shatnawi³

2007

2007 Canadian Conference on Electrical and Computer Engineering

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Abstract─ In recent years a great deal of research has been conducted in the area of scheduling of DSP data flow graphs (DFG) onto multiprocessing systems. In this paper, a new processor allocation technique is proposed. Both heterogeneous and general-purpose functional units are used during the resource allocation process. The proposed technique provides the designer with more flexibility to explore the design space by using different types of processing modules for the same task. The proposed allocation technique leads to different multiprocessor architectures for a given rate-optimal schedule of a DSP data flow graph. A satisfactory function is used to infer the quality of the obtained architectures in terms of the area and utilization of each of them. The proposed algorithm is applied to a well-known benchmark problem of DSP filter. It is seen that moving from a fully-homogenous to a fully-heterogeneous multiprocessor architecture results in decreasing the area of the design. However, a hybrid multiprocessor architecture brings about a trade off between the area and the utilization.

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Dynamically Reconfigurable Adaptable MultiModule Based Synthesis of DSP Data Flow Graphs

Itradat¹,

Ahmad²,

Shatnawi³

2007

2007 Canadian Conference on Electrical and Computer Engineering

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Scheduling of DSP Algorithms onto Heterogeneous-Multiprocessors with Inter-Processor Communication

Cited by 5 publications

References 5 publications

Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs

Minimization of I/O Delay in the architectural synthesis of DSP data flow graphs

A Processor Allocation of DSP Applications Onto Heterogeneous Multiprocessor Architectures

Dynamically Reconfigurable Adaptable MultiModule Based Synthesis of DSP Data Flow Graphs

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