Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics

Gottlob, H. D. B.; Schmidt, M.; Stefani, Andrea; Lemme, Max C.; Kurz, H.; Mitrović, Ivona Z.; Davey, W.; Hall, Steve; Werner, M.; Chalker, Paul R.; Cherkaoui, Karim; Hurley, Paul K.; Piscator, Johan; Engström, Olof; Newcomb, S. B.

doi:10.1016/j.mee.2009.03.084

Cited by 17 publications

(14 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…43,44 Figures 5(b) and 5(c) indicate that for deposition pressures of 0.75 and 1.0 mbar, the dielectric stack also consists of an amorphous GdSiO x layer and a poly-Gd 2 O 3 layer whose thicknesses decrease with deposition pressure. Figure 5(d) shows that for 1.3 mbar, only an amorphous GdSiO x film is found.…”

Section: A Structural Characterizationmentioning

confidence: 99%

Optimization of gadolinium oxide growth deposited on Si by high pressure sputtering

Feijoo

Pampillón

Andrés

2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

View full text Add to dashboard Cite

Articles you may be interested inOptimization of in situ plasma oxidation of metallic gadolinium thin films deposited by high pressure sputtering on silicon J.Embedded argon as a tool for sampling local structure in thin plasma deposited aluminum oxide films Structural, optical, and electrical characterization of gadolinium oxide films deposited by low-pressure metalorganic chemical vapor deposition High j gadolinium oxide thin layers were deposited on silicon by high-pressure sputtering (HPS). In order to optimize the properties for microelectronics applications, different deposition conditions were used. Ti (scavenger) and Pt (nonreactive) were e-beam evaporated to fabricate metal-insulator-semiconductor (MIS) devices. According to x-ray diffraction, x-ray photoelectron spectroscopy, and Fourier-transform infrared spectroscopy, polycrystalline stoichiometric Gd 2 O 3 films were obtained by HPS. The growth rate decreases when increasing the deposition pressure. For relatively thick films (40 nm), a SiO x interface as well as the formation of a silicate layer (GdSiO x ) is observed. For thinner films, in Ti gated devices the SiO x interface disappears but the silicate layer extends over the whole thickness of the gadolinium oxide film. These MIS devices present lower equivalent oxide thicknesses than Pt gated devices due to interface scavenging. The density of interfacial defects D it is found to decrease with deposition pressure, showing a reduced plasma damage of the substrate surface for higher pressures. MIS with the dielectric deposited at higher pressures also present lower flatband voltage shifts DV FB in the C HF -V G hysteresis curves.

show abstract

Section: A Structural Characterizationmentioning

confidence: 99%

Optimization of gadolinium oxide growth deposited on Si by high pressure sputtering

Feijoo

Pampillón

Andrés

2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

View full text Add to dashboard Cite

show abstract

“…15,16 Si surfaces were prepared by RCA cleaning followed by dry thermal oxidation to form SiO 2 interlayers $4 nm thick. 10 nm thick Gd 2 O 3 films were then deposited by electron beam evaporation from granular Gd 2 O 3 at a deposition rate of 0.01 nm/s and molecular nitrogen was present during deposition.…”

mentioning

confidence: 99%

“…The samples then underwent RTA for 1 s at 900 C to form GdSiO x from the initial Gd 2 O 3 /SiO 2 bilayer. 15,16 TiN electrodes (50 nm thick) were deposited by reactive sputtering from Ti, and circular capacitors of various areas were defined using a lift-off process. Finally, backside contacts were formed by deposition of Al.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Observation of peripheral charge induced low frequency capacitance-voltage behaviour in metal-oxide-semiconductor capacitors on Si and GaAs substrates

O’Connor

Cherkaoui

Monaghan

et al. 2012

Journal of Applied Physics

Self Cite

View full text Add to dashboard Cite

We report on experimental observations of room temperature low frequency capacitance-voltage (CV) behaviour in metal oxide semiconductor (MOS) capacitors incorporating high dielectric constant (high-k) gate oxides, measured at ac signal frequencies (2 kHz to 1 MHz), where a low frequency response is not typically expected for Si or GaAs MOS devices. An analysis of the inversion regions of the CV characteristics as a function of area and ac signal frequency for both n and p doped Si and GaAs substrates indicates that the source of the low frequency CV response is an inversion of the semiconductor/high-k interface in the peripheral regions outside the area defined by the metal gate electrode, which is caused by charge in the high-k oxide and/or residual charge on the high-k oxide surface. This effect is reported for MOS capacitors incorporating either MgO or GdSiOx as the high-k layers on Si and also for Al2O3 layers on GaAs(111B). In the case of NiSi/MgO/Si structures, a low frequency CV response is observed on the p-type devices, but is absent in the n-type devices, consistent with positive charge (>8 × 1010 cm−2) on the MgO oxide surface. In the case of the TiN/GdSiOx/Si structures, the peripheral inversion effect is observed for n-type devices, in this case confirmed by the absence of such effects on the p-type devices. Finally, for the case of Au/Ni/Al2O3/GaAs(111B) structures, a low-frequency CV response is observed for n-type devices only, indicating that negative charge (>3 × 1012 cm−2) on the surface or in the bulk of the oxide is responsible for the peripheral inversion effect.

show abstract

“…High-k dielectric gadolinium silicate (GdSiO) films with large band offsets to silicon, a dielectric constant of 16 provide an attractive scaling potential for future low power applications [1][2] [3]. Thermal stability up to 1000°C -a key issue for gate first integration -has been demonstrated for uncapped films in combination with titanium nitride (TiN) electrodes [1][2] [4].…”

Section: Introductionmentioning

confidence: 99%

Mobility extraction in sub 10nm nanowire nMOSFETs with gadolinium-silicate as gate dielectric

Schmidt

Gottlob

Bolten

et al. 2011

Ulis 2011 Ultimate Integration on Silicon

Self Cite

View full text Add to dashboard Cite

Gadolinium-silicate (GdSiO) as high-k dielectric in sub 10nm gate first nanowire (NW) nMOSFETs is investigated. NW-and UTB-nMOSFETs with conventional SiO 2 /Poly-Si gate stacks have been fabricated and compared with GdSiO/TiN NW nMOSFETs. Specific nMOSFETs with multiple NWs in parallel have been used to extract the effective mobility by split-CV method and to eliminate the series resistance to correct the measured data. IntroductionHigh-k dielectric gadolinium silicate (GdSiO) films with large band offsets to silicon, a dielectric constant of 16 provide an attractive scaling potential for future low power applications [1][2][3]. Thermal stability up to 1000°C -a key issue for gate first integration -has been demonstrated for uncapped films in combination with titanium nitride (TiN) electrodes [1][2][4].In addition to an excellent control of V th one dimensional nanostructures are potentially attractive increase of severely depressed SCE and higher I On /I Off ratios [5] [6].A major disadvantage of UTB SOI, FinFETs and NW MOSFETs however, is the concurrent increase of parasitic source to drain resistances, especially if silicon the thickness drops below 10 nm of the silicon film. This inherent feature may eventually be solved by selective epitaxy and/or silicided source drain leads [7][8]. One of the key features, the inversion channel mobility of MOSFETs, can not be extracted from standard split C/V measurements accurately if the high access resistance problem is not addressed appropriately [9].For UTB structures, a special mobility test structure has been proposed and applied to UTB SOI and sSOI devices [9]-[12]. This structure features contacts to the inversion channel to allow four-probe measurements where the series resistance effects can be eliminated. For NW-or FinFETs, however, this structure can not be employed as an inversion layer contact would disrupt the main transistor channel on the Fin/NW sidewall. Instead, we propose to use a different approach with several devices to extract the real series resistance and to correct the measured split C/V data. Experimental Device LayoutKey for the correct mobility (μ eff ) extraction by the split CV technique according to equation 1 is the exact knowledge of the voltage drop V DS inside the channel and the exact measurement of the inversion charge density Q inv . The other parameters in equ. 1 are the gate length L, the gate width W (extracted from TEM images) and the measured drain source current I DS .) (The proposed design for NW MOSFETs feature two "sense" contacts in addition to the conventional source and drain contacts (V L/R , Fig. 1). Furthermore, to address large gate areas and therefore to measure an adequate gate to channel capacitance, very long (L G =100μm) and multiple NWs in parallel are fabricated for split CV method. Fig. 1: Optical micrograph (top view) of a SOI NW nMOSFET with 400 NWs in parallel and additional contacts close to the channel (V L/R ). Q inv can be determined directly by integrating the gate channel capacitance C gc mea...

show abstract

Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics

Cited by 17 publications

References 16 publications

Optimization of gadolinium oxide growth deposited on Si by high pressure sputtering

Optimization of gadolinium oxide growth deposited on Si by high pressure sputtering

Observation of peripheral charge induced low frequency capacitance-voltage behaviour in metal-oxide-semiconductor capacitors on Si and GaAs substrates

Mobility extraction in sub 10nm nanowire nMOSFETs with gadolinium-silicate as gate dielectric

Contact Info

Product

Resources

About