Scalable don't-care-based logic optimization and resynthesis

Abstract

We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on industrial designs. The approach uses don't cares computed for a window surrounding a node and can take into account external don't cares (e.g. unreachable states). It uses a SAT solver and interpolation to find a new representation for a node. This representation can be in terms of inputs from other nodes in the window thus effecting Boolean re-substitution. Experimental results on 6-input LUT networks after high effort synthesis show substantial reductions in area and delay. When applied to 20 large academic benchmarks, the LUT count and logic level is reduced by 45.0% and 12.2%, respectively. The longest runtime for synthesis and mapping is about two minutes. When applied to a set of 14 industrial benchmarks ranging up to 83K 6-LUTs, the LUT count and logic level is reduced by 11.8% and 16.5%, respectively. Experimental results on 6-input LUT networks after high-effort synthesis show substantial reductions in area and delay. The longest runtime is about 30 minutes.

Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization

“…Recently, it has become popular in verification and logic synthesis [2], [11], [12]. Craig interpolation theorem states that given a pair of Boolean formulas A and B, such that A ∧ B = f alse, there exists an intermediate formula I, such that A ⇒ I and I ⇒B.…”

“…There are several applications of Craig interpolation, such as model checking [11], functional dependency [12] and Boolean relation determination [7]. McMillan [11] utilized Craig interpolation to generate an approximated image operator that can be used in symbolic checking.…”

“…McMillan [11] utilized Craig interpolation to generate an approximated image operator that can be used in symbolic checking. Mishchenko et al [12] proposed a logic optimization technique which uses interpolation to compute synthesis functional dependency. In [7], Jiang et al addressed the scalability issue and demonstrated a method to extend determination capacity through interpolation.…”

Boolean Decomposition for AIG Optimization

“…Still, these techniques are usually constrained by single output transformations, and iterations with technology mapping [7,12] are often used to improve structurally biased results.…”

Area-efficient FPGA logic elements: Architecture and synthesis

“…We present straightforward techniques to map circuits into the proposed architectures. While recent work on technology mapping and logic synthesis has focused on reducing the number of LUTs needed to implement circuits [5,6], our work is unique in that we take an architectural approach wherein we use logic synthesis concepts to influence the design of the logic element architecture itself. Our experimental results demonstrate that with the proposed logic element architectures, silicon area can be reduced without any appreciable impact to circuit delaya result we believe will keenly interest FPGA architects and vendors.…”