Scalable architecture for word HMM-based speech recognition and VLSI implementation in complete system

Yoshizawa, Shingo; Wada, Naoya; Hayasaka, Noboru; Miyanaga, Yoshikazu

doi:10.1109/tcsi.2005.854408

Cited by 63 publications

(49 citation statements)

References 12 publications

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“…However, some of them can only support a small vocabulary [3,4,5,7], some of them are limited in speed [3,5], some others consume much power because of numerous external memory access [4,6]. In our prior work [8,9], we employs some algorithm optimization and specialized cache architecture to reduce the external memory bandwidth, which successfully achieves realtime continuous speech recognition with 60-kWord models.…”

Section: Introductionmentioning

confidence: 99%

A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI

Miyamoto

Matsuda

et al. 2014

IEICE Electron. Express

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This paper describes a low-power VLSI chip for speakerindependent 60-kWord continuous speech recognition. We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. Measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02× and 2.25× times faster than real-time at 200 MHz using the bigram and trigram language models, respectively.

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Section: Introductionmentioning

confidence: 99%

A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI

Miyamoto

Matsuda

et al. 2014

IEICE Electron. Express

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“…On the other hand, it requires high calculation cost and many training databases for all target speech phrases. By using an efficient LSI design for a speech recognition system, the authors have been able to realize real-time speech recognition with low power consumption even although the total calculation cost becomes high [8], [11], [13], [17]. As advanced technology using the above phrase based speech recognition techniques, a speech communication system has been proposed, and this paper presents an overview of this system and its performance.…”

Section: Introductionmentioning

confidence: 99%

A Robust Speech Communication into Smart Info-Media System

Miyanaga

Takahashi

Yoshizawa

2013

IEICE Trans. Fundamentals

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SUMMARYThis paper introduces our developed noise robust speech communication techniques and describes its implementation to a smart info-media system, i.e., a small robot. Our designed speech communication system consists of automatic speech detection, recognition, and rejection. By using automatic speech detection and recognition, an observed speech waveform can be recognized without a manual trigger. In addition, using speech rejection, this system only accepts registered speech phrases and rejects any other words. In other words, although an arbitrary input speech waveform can be fed into this system and recognized, the system responds only to the registered speech phrases. The developed noise robust speech processing can reduce various noises in many environments. In addition to the design of noise robust speech recognition, the LSI design of this system has been introduced. By using the design of speech recognition application specific IC (ASIC), we can simultaneously realize low power consumption and real-time processing. This paper describes the LSI architecture of this system and its performances in some field experiments. In terms of current speech recognition accuracy, the system can realize 85-99% under 0-20 dB SNR and echo environments.

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“…Although processor-based approaches offer flexibility, realtime recognition tasks using state-of-the-art recognition algorithms exceed the performance level of current embedded processors, and require modern high-performance processors that consume far more power than dedicated hardware [2]- [5]. Dedicated hardware, which is optimized for low-power, real-time recognition tasks, is more suitable for implementing natural human interfaces in low-power mobile embedded systems.…”

Section: Introductionmentioning

confidence: 99%

“…Fast and memory-efficient VLSI architectures with small number of registers and processing elements are required for the development of well-optimized embedded systems with capable future human interfaces. VLSI architectures optimized for recognition tasks with low power dissipation have been developed [2]- [6]. Yoshizawa et al investigated a block-wise parallel processing method for output probability computations of continuous hidden Markof models (HMMs) and proposed a low power, high-speed VLSI architecture [2]- [4].…”

Section: Introductionmentioning

confidence: 99%

“…VLSI architectures optimized for recognition tasks with low power dissipation have been developed [2]- [6]. Yoshizawa et al investigated a block-wise parallel processing method for output probability computations of continuous hidden Markof models (HMMs) and proposed a low power, high-speed VLSI architecture [2]- [4]. Output probability computations are the most time-consuming part of HMM-based recognition systems.…”

Section: Introductionmentioning

confidence: 99%

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A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing

Nakamura

Yamamoto

Takagi

et al. 2010

IEICE Trans. Inf. & Syst.

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SUMMARYIn this paper, a fast and memory-efficient VLSI architecture for output probability computations of continuous Hidden Markov Models (HMMs) is presented. These computations are the most timeconsuming part of HMM-based recognition systems. High-speed VLSI architectures with small registers and low-power dissipation are required for the development of mobile embedded systems with capable human interfaces. We demonstrate store-based block parallel processing (StoreBPP) for output probability computations and present a VLSI architecture that supports it. When the number of HMM states is adequate for accurate recognition, compared with conventional stream-based block parallel processing (StreamBPP) architectures, the proposed architecture requires fewer registers and processing elements and less processing time. The processing elements used in the StreamBPP architecture are identical to those used in the StoreBPP architecture. From a VLSI architectural viewpoint, a comparison shows the efficiency of the proposed architecture through efficient use of registers for storing input feature vectors and intermediate results during computation.

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Scalable architecture for word HMM-based speech recognition and VLSI implementation in complete system

Cited by 63 publications

References 12 publications

A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI

A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI

A Robust Speech Communication into Smart Info-Media System

A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing

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