SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

Wang, Weixun; Mishra, Prabhat; Gordon‐Ross, Ann

doi:10.1109/vlsi.design.2009.66

Cited by 15 publications

(7 citation statements)

References 15 publications

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“…The tuning modes exhibit similar trends for both the data and instruction caches. As expected, the aggressive mode (as in prior work [9] [11]) achieved the highest average energy savings of 39.76% and 34.98% for the data and instruction caches, respectively. Even though the moderate and conservative modes explored fewer configurations, these modes still achieved average energy savings of 20.68% and 25.14%, and 19.00% and 23.49%, respectively.…”

Section: B Evaluation Methodologysupporting

confidence: 79%

“…We incorporated an exhaustive mode to search the complete design space, regardless of QoS degradations. Additionally, the exhaustive mode reveals the energy savings that would be obtained using prior work [9]. However, that prior work required a priori knowledge of the applications to alleviate tuning overhead.…”

Section: B Evaluation Methodologymentioning

confidence: 99%

“…Configurable parameters' values can be tuned/adjusted to the best configuration that most closely adheres to locality requirements, and thus most closely adheres to the energy and QoS expectations. However, determining the best configuration imposes tuning overhead [6] that degrades QoS or requires static application profiling [9] that may not scale to unknown applications, which limits applicability to the rapidly expanding number of, largely third-party, applications.…”

Section: Introductionmentioning

confidence: 99%

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Quality of Service-Aware, Scalable Cache Tuning Algorithm in Consumer-based Embedded Devices

Alsafrjalani

Gordon‐Ross

2016

Proceedings of the 26th Edition on Great Lakes Symposium on VLSI

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To meet energy and quality of service (QoS) constraints in consumer/user-based embedded devices (CEDs), configurable caches can be tuned to a best configuration that consumes the least amount of energy while adhering to QoS expectations. However, due to disparate consumer QoS expectations and a myriad of unknown, third-party CED applications, tuning caches in CEDs is very challenging. In this paper, we propose a quality of service-aware, scalable tuning algorithm for configurable caches, which requires no a priori knowledge of applications or design-time efforts.

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Section: B Evaluation Methodologysupporting

confidence: 79%

Section: B Evaluation Methodologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Quality of Service-Aware, Scalable Cache Tuning Algorithm in Consumer-based Embedded Devices

Alsafrjalani

Gordon‐Ross

2016

Proceedings of the 26th Edition on Great Lakes Symposium on VLSI

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“…Alternatively to scheduling applications to disparate heterogeneous cores, researchers also tuned configurable hardware to adhere to the disparate applications' requirements. Prior work [10,[28][29][30] leveraged configurable caches to reduce energy and/or increase performance; however, many of these works required designers' efforts to determine the best configuration. Wang et al [28] profiled the applications offline and stored the best configuration information in a lookup table to be used during runtime.…”

Section: Application Scheduling and Core Tuningmentioning

confidence: 99%

“…Prior work [10,[28][29][30] leveraged configurable caches to reduce energy and/or increase performance; however, many of these works required designers' efforts to determine the best configuration. Wang et al [28] profiled the applications offline and stored the best configuration information in a lookup table to be used during runtime. To meet real-time deadlines, the system looked up the application's performance information in the lookup table and tuned the cache to the highest performance configuration.…”

Section: Application Scheduling and Core Tuningmentioning

confidence: 99%

Scheduling and Tuning for Low Energy in Heterogeneous and Configurable Multicore Systems

Alsafrjalani

Gordon‐Ross

2018

Computers

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Heterogeneous and configurable multicore systems provide hardware specialization to meet disparate application hardware requirements. However, effective multicore system specialization can require a priori knowledge of the applications, application profiling information, and/or dynamic hardware tuning to schedule and execute applications on the most energy efficient cores. Furthermore, even though highly disparate core heterogeneity and/or highly configurable parameters with numerous potential parameter values result in more fine-grained specialization and higher energy savings potential, these large design spaces are challenging to efficiently explore. To address these challenges, we propose a novel configuration-subsetted heterogeneous and configurable multicore system, wherein each core offers a small subset of the design space, and propose a novel scheduling and tuning (SaT) algorithm to efficiently exploit the energy savings potential of this system. Our proposed architecture and algorithm require no a priori application knowledge or profiling, and incur minimal runtime overhead. Results reveal energy savings potential and insights on energy trade-offs in heterogeneous, configurable systems.

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