Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test

Abstract

Abstract-Formal CAD tools operate on mathematical models describing the sequential behavior of a VLSI design. With the growing size and state-space of modern digital hardware designs, the conciseness of this mathematical model is of paramount importance in extending the scalability of those tools, provided that the compression does not come at the cost of reduced performance. Quantified Boolean Formula satisfiability (QBF) is a powerful generalization of Boolean satisfiability (SAT). It also belongs to the same complexity class as many CAD problems dealing with sequential circuits, which makes it a natural candidate for encoding such problems. This work proposes a succinct QBF encoding for modeling sequential circuit behavior. The encoding is parametrized and further compression is achieved using time-frame windowing. Comprehensive hardware constructions are used to illustrate the proposed encodings. Three notable CAD problems, namely bounded model checking, design debugging and sequential test pattern generation, are encoded as QBF instances to demonstrate the robustness and practicality of the proposed approach. Extensive experiments on OpenCore circuits show memory reductions in the order of 90% and demonstrate competitive run-times compared to state-of-the-art SAT techniques. Furthermore, the number of solved instances is increased by 16%. Admittedly, this work encourages further research in the use of QBF in CAD for VLSI.

Multiple clock domain synchronization in a QBF-based verification environment

“…. , Vn, the QBF problem asks whether Φ can be satisfied through a proper assignment to the variables [5]. A satisfying assignment (SAT) to Φ yields Φ = 1, while an unsatisfying one (UNSAT) yields Φ = 0.…”

“…2. Inside the dashed boxes, a robust QBF-based ILA encoding is presented [5]. Combinational logic clocked by clock i is represented by the transition relation Tc i (sc i , s …”

“…The two multiplexers around Tc i are used to connect the next state assignment of the current cycle to the current state assignment of the next cycle through the use of the select line cyclec i . In this sense, the value of the select line determines the state of a clock domain at a particular cycle and allows one to model the sequential behavior of the design [5].…”

“…Conceptually, the global clock acts as a data probe where its positive edge indicates a state transition of some clock domain in the design. Following this, an iterative logic array (ILA) is generated [5], an action also knows as "circuit unrolling". However, in the presence of multiple clocks, a clock may have to wait for computation from another clock.…”

“…With large circuits, the memory capacity becomes a concern because ILA memory size scales with the number of time-frames. Over many cycles the memory requirements may become substantial [5]. This realization prompts into developing memory-efficient methodologies.…”